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ST6380,ST6381,ST6382, ST6383,ST6388,ST6389
8-BIT MCUs WITH ON-SCREEN-DISPLAY FOR TV TUNING
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4.5 to 6V supply operating range 8MHz Maximum Clock Frequency User Program ROM: up to 20140 bytes Reserved Test ROM: up to 340 bytes Data ROM: user selectable size Data RAM: 256 bytes Data EEPROM: 384 bytes 42-Pin Shrink Dual in Line Plastic Package Up to 22 software programmable general purpose Inputs/Outputs, including 2 direct LED driving Outputs Two Timers each including an 8-bit counter with a 7-bit programmable prescaler Digital Watchdog Function Serial Peripheral Interface (SPI) supporting SPSDIP42 BUS/ I 2 C BUS and standard serial protocols SPI for external frequency synthesis tuning (Refer .com to end of Document for Ordering Information) 14-bit counter for voltage synthesis tuning Up to Six 6-Bit PWM D/A Converters One 8 bits D/A Converter with 7 analog inputs Five interrupt vectors (IRIN/NMI, Timer 1 & 2, VSYNC, PWR /ADC) DEVICE SUMMARY On-chip clock oscillator ROM 8 Lines by 20 Characters On-Screen Display DEVICE D/A Converter (Bytes) Generator with 192 Characters in one bank. ST6380 8K 6 14X18 OSD characters with rounding function. ST6381 8K 4 All ROM types are supported by pin-to-pin ST6382 16K 6 EPROM and OTP versions with programmable OSD fonts. ST6383 16K 4 ST6388 20K 6 The development tool of the ST6380, 81, 82, 83, 88 and ST6389 microcontrollers consists of ST6389 20K 4 the ST638X-EMU2 emulation and development system to be connected via a standard parallel line to an MS-DOS Personal Computer.
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Table of Contents
ST6380, ST6381, ST6382, ST6383, ST6388, ST6389 . . . . . . . . 1
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.1 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3.4 Data RAM/EEPROM/OSD RAM Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . 18 3.1 ON-CHIP CLOCK OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.1 RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.4 Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.5 MCU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 20 20 20 21 21 21 21 22 24 24 25 25 26 28 28 29 31 31 31 32 33 34 34 34
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3.3.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 STOP Mode . . . . . . . . . . . . .com . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............... 3.3.3 Exit from WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION . . . . . . . . . . . . . . . . . . . . 3.5.1 Interrupt Vectors/Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.3 Interrupt Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.4 Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.5 ST638x Interrupt Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 Details of I/O Ports . . . . . . . . . . . 4.1.2 I/O Pin Programming . . . . . . . . . 4.1.3 Input/Output Configurations . . . . 4.1.4 I/O Port Registers . . . . . . . . . . . 4.2 TIMERS . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 4.2.2 4.2.3 4.2.4 ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ....... ....... ....... ....... .......
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3.5 INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Status Control Registers (TSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Counter Registers (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Prescaler Registers (PSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
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4.3 SERIAL PERIPHERAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.3.1 S-BUS/I2C BUS Protocol Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 S-BUS/I2C BUS Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3 Compatibility S-BUS/I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4 STD SPI Protocol (Shift Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.5 SPI Data/Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 14-BIT VOLTAGE SYNTHESIS TUNING PERIPHERAL . . . . . . . . . . . . . . . . . . . . . . . . . . 35 38 40 41 41 44
4.4.1 Output Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.4.2 VS Tuning Cell Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.5 6-BIT PWM D/A CONVERTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.6 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.6.1 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.7 DEDICATED LATCHES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.8 ON-SCREEN DISPLAY (OSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.8.1 Format Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.2 Format Character Register (FT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.3 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 MIRROR REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 50 57 58
4.10 XOR REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 .com 6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.3 CUSTOMER EEPROM INITIAL CONTENTS: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.4 OSD TEST CHARACTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.5 ORDERING INFORMATION TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
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ST63E88,ST63T88, ST63E89,ST63T89 . . . . . . . . . . . . . . . . . . 73
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1.1 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 1.2 EPROM/OTP DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 1.3 EPROM ERASING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 2 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 2.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 2.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 2.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 2.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 2.5 OSD TEST CHARACTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
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ST6380, ST6381, ST6382, ST6383, ST6388, ST6389
1 GENERAL DESCRIPTION
1.1 INTRODUCTION The ST6380, ST6381, ST6382, ST6383, ST6388, ST6389 microcontrollers are members of the 8-bit HCMOS ST638x family, a series of devices specially oriented to TV applications. Different ROM size and peripheral configurations are available to give the maximum application and cost flexibility. All ST638x members are based on a building block approach: a common core is surrounded by a combination of on-chip peripherals (macrocells) available from a standard library. These peripherals are designed with the same Core technology providing full compatibility and short design time. Many of these macrocells are specially dedicated to TV applications. The macrocells of the ST638x family are: two Timer peripherals each including Table 1. Device Summary
Device ST6380 ST6381 ST6382 ST6383 ST6388 ST6389 ROM (Bytes) 8K 8K 16K 16K 20K 20K RAM (Bytes) 256 256 256 256 256 256 EEPROM ADC VS (Bytes) 384 Yes Yes 384 Yes Yes 384 Yes Yes 384 Yes Yes 384 Yes Yes .com 384 Yes Yes D/A 6 4 6 4 6 4 Colour Pins 3 3 3 3 3 3 Emulating Devices ST63T88, ST63T89, ST63T88, ST63T89, ST63T88, ST63T89, ST63E88 ST63E89 ST63E88 ST63E89 ST63E88 ST63E89
an 8-bit counter with a 7-bit software programmable prescaler (Timer), a digital hardware activated watchdog function (DHWD), a 14-bit voltage synthesis tuning peripheral, a Serial Peripheral Interface (SPI), up to six 6-bit PWM D/A converters, up to 7 8-bit A/D Converter, an on-screen display (OSD) with 20 characters per line and 192 characters (in one bank). In addition the following memory resources are available: program ROM (up to 20K), data RAM (256 bytes), EEPROM (384 bytes). Refer to pin configurations figures and to ST638x device summary (Table 1) for the definition of ST638x family members and a summary of differences among the different types.
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ST6380, ST6381, ST6382, ST6383, ST6388, ST6389
Figure 1. Block Diagram
PORT A TEST TEST INTERRUPT Inputs DATA ROM USER SELECTABLE DATA RAM 256 Bytes DATA EEPROM 384 Bytes PORT B & A/D inputs PORT C
PA0 - PA7* PB0 - PB6*
IRIN/PC6
USER PROGRAM MEMORY UP TO 20KBytes
Serial Peripheral Interface
PC2, PC4 - PC7* PC0/SCL PC1/SDA PC3/SEN
TIMER 1
TIMER 2
PC STACK LEVEL 1 STACK LEVEL 2 STACK LEVEL 3 STACK LEVEL 4 8 BIT CORE
Digital Watchdog Timer D/A Outputs DA0 - DA5*
VS Output On-Screen Display
VS* R, G, B, BLANK HSYNC, VSYNC
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STACK LEVEL 5 STACK LEVEL 6 POWER SUPPLY OSCILLATOR
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RESET
VDD VSS
OSCin OSCout
RESET
OSDOSCout
OSDOSCin VR01753
*Refer to Pin Description for Additional Information
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ST6380, ST6381, ST6382, ST6383, ST6388, ST6389
1.2 PIN DESCRIPTION VDD and VSS. Power is supplied to the MCU using open-drain (5V drive) in output mode while PC4 to PC7 are open-drain with 12V drive and the input these two pins. V DD is power and VSS is the ground connection. pull-up options does not exist on these four pins. PC0, PC1 and PC3 lines when in output mode are OSCin, OSCout. These pins are internally con"ANDed" with the SPI control signals and are all nected to the on-chip oscillator circuit. A quartz open-drain. PC0 is connected to the SPI clock sigcrystal or a ceramic resonator can be connected nal (SCL), PC1 with the SPI data signal (SDA) between these two pins in order to allow the corwhile PC3 is connected with SPI enable signal rect operation of the MCU with various stability/ (SEN, used in S-BUS protocol). Pin PC4 and PC6 cost trade-offs. The OSCin pin is the input pin, the can also be inputs to software programmable edge OSCout pin is the output pin. sensitive latches which can generate interrupts; RESET. The active low RESET pin is used to start PC4 can be connected to Power Interrupt while the microcontroller to the beginning of its program. PC6 can be connected to the IRIN/NMI interrupt Additionally the quartz crystal oscillator will be disline. abled when the RESET pin is low to reduce power DA0-DA5. These pins are the six PWM D/A outconsumption during reset phase. puts of the 6-bit on-chip D/A converters. These TEST. The TEST pin must be held at VSS for norlines have open-drain outputs with 12V drive. The mal operation. output repetition rate is 31.25KHz (with 8MHz clock). PA0-PA7. These 8 lines are organized as one I/O port (A). Each line may be configured as either an OSDOSCin, OSDOSCout. These are the On input with or without pull-up resistor or as an outScreen Display oscillator terminals. An oscillation put under software control of the data direction capacitor and coil network have to be connected to register. Pins PA4 to PA7 are configured as openprovide the right signal to the OSD. drain outputs (12V drive). On PA4-PA7 pins the inHSYNC, VSYNC. These are the horizontal and put pull-up option is not available while PA6 and vertical synchronization pins. The active polarity of PA7 have additional current driving capability these pins to the OSD macrocell can be selected (25mA, V OL:1V). PA0 to PA3 pins are configured by the .comuser as ROM mask option. If the device is as push-pull. specified to have negative logic inputs, then these PB0-PB6. These 7 lines are organized as one I/O signals are low the OSD oscillator stops. If the deport (B). Each line may be configured as either an vice is specified to have positive logic inputs, then input with or without internal pull-up resistor or as when these signals are high the OSD oscillator an output under software control of the data direcstops. VSYNC is also connected to the VSYNC intion register. In addition any pin can be configured terrupt. by software as the input to the Analog to Digital R, G, B, BLANK. Outputs from the OSD. R, G and converter. In this case only one pin should be conB are the color outputs while BLANK is the blankfigured at any time to avoid conflicts. ing output. All outputs are push-pull. PC0-PC7. These 8 lines are organized as one I/O VS. This is the output pin of the on-chip 14-bit voltport (C). Each line may be configured as either an age synthesis tuning cell (VS). The tuning signal input with or without internal pull-up resistor or as present at this pin gives an approximate resolution an output under software control of the data direcof 40KHz per step over the UHF band. This line is tion register. Pins PC0 to PC3 are configured as a push-pull output with standard drive.
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ST6380, ST6381, ST6382, ST6383, ST6388, ST6389
Figure 2. ST6380, 82, 88 Pin Configuration
DA0 DA1 DA2 DA3 DA4 DA5 AD1/PB1 AD2/PB2 AD3/PB3 AD4/PB4 AD5/PB5 AD6/PB6 PA0 PA1 PA2 PA3 PA4 PA5 PA6 (HD0) PA7 (HD1) VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VDD PC0/SCL PC1/SDA PC2 PC3/SEN PC4/PWRIN PC5 PC6/IRIN VS RESET OSCout OSCin TEST/VPP (1) OSDOSCout OSDOSCin VSYNC HSYNC BLANK B G R
VR01375
Figure 3. ST6381, 83, 89 Pin Configuration
VS DA1 DA2 DA3 DA4 AD0/PB0 AD1/PB1 AD2/PB2 AD3/PB3 AD4/PB4 AD5/PB5 AD6/PB6 PA0 PA1 PA2 PA3 PA4 PA5 PA6 (HD0) PA7 (HD1) VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VDD PC0/SCL PC1/SDA PC2 PC3/SEN PC4/PWRIN PC5 PC6/IRIN PC7 RESET OSCout OSCin TEST/VPP (1) OSDOSCout OSDOSCin VSYNC HSYNC BLANK B G R
VR01375E
(1) This pin is also the VPP input for OTP/EPROM devices
(1) This pin is also the VPP input for OTP/EPROM devices
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Table 2. Pin Summary
Pin Function DA0 to DA5 VS R, G, B, BLANK HSYNC, VSYNC OSDOSCin OSDOSCout TEST OSCin OSCout RESET PA0- PA3 PA4- PA5 PA6- PA7 PB0- PB6 PC0- PC3 PC4- PC7 VDD, VSS
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Description Output, Open- Drain, 12V Output, Push- Pull Output, Push- Pull Input, Pull- up, Schmitt Trigger Input, High Impedance Output, Push- Pull Input, Pull- Down Input, Resistive Bias, Schmitt Trigger to Reset Logic Only Output, Push- Pull Input, Pull- up, Schmitt Trigger Input I/ O, Push- Pull, Software Input Pull- up, Schmitt Trigger Input 5mA I/ O, Open- Drain, 12V, No Input Pull- up, Schmitt Trigger Input I/ O, Open- Drain, 12V, No Input Pull- up, Schmitt Trigger Input, High Drive 25mA I/ O, Push- Pull/Open Drain, Software Input Pull- up, Schmitt Trigger Input, Analog input I/ O, Open- Drain, 5V, Software Input Pull- up, Schmitt Trigger Input 5mA I/ O, Open- Drain, 12V, No Input Pull- up, Schmitt Trigger Input 5mA Power Supply Pins
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ST6380, ST6381, ST6382, ST6383, ST6388, ST6389
1.3 MEMORY SPACES seen as static space. Table 3 gives the different The MCU operates in three different memory codes that allows the selection of the correspondspaces: Stack Space, Program Space and Data ing banks. Note that, from the memory point of Space. view, the Page 1 and the Static Page represent 1.3.1 Stack Space the same physical memory: it is only a different The stack space consists of six 12 bit registers that way of addressing the same location. On the are used for stacking subroutine and interrupt reST6388 and ST6389, a total of 20480 bytes of turn addresses plus the current program counter ROM have been implemented; 20140 bytes are register. available as User ROM while 340 bytes are reserved for testing. 1.3.2 Program Space Figure 4. 20K-Byte Program Space Addressing The program space is physically implemented in the ROM and includes all the instructions that are Program to be executed, as well as the data required for the counter space immediate addressing mode instructions, the re4FFFh 0000h served test area and the user vectors. It is addressed thanks to the 12-bit Program Counter reg0FFFh ister (PC register) and the ST6 Core can directly Page 1 address up to 4K bytes of Program Space. Nevertheless, the Program Space can be extended by Static the addition of 2Kbyte memory banks as it is Page shown in Figure 5, in which the 20K bytes memory 0800h is described. These banks are addressed by point07FFh ing to the 000h-7FFh locations of the Program Space thanks to the Program Counter, and by writPage 1 ... Page 0 ing the appropriate code in the Program ROM Page 9 Static Page Page Register (PRPR) located at address CAh in the Data Space. Because interrupts and common 0000h subroutines should be available all the time only the lower 2K byte of the 4K program space are .com bank switched while the upper 2K byte can be Figure 5. Memory Addressing Diagram
STACK SPACE PROGRAM SPACE DATA SPACE
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0000h PROGRAM COUNTER ROM STACK LEVEL 1 STACK LEVEL 2 STACK LEVEL 3 STACK LEVEL 4 STACK LEVEL 5 STACK LEVEL 6 ROM 07FFh 0800h 0-63
000h RAM / EEPROM BANKING AREA 03Fh 040h DATA ROM WINDOW 07Fh 080h 081h 082h 083h 084h 0C0h X REGISTER Y REGISTER V REGISTER W REGISTER RAM DATA ROM WINDOW SELECT DATA RAM BANK SELECT 0FFh ACCUMULATOR
0FF0h INTERRUPT & RESET VECTORS 0FFFh
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MEMORY SPACES (Cont'd) Program ROM Page Register (PRPR) Address: CAh - Write only Reset Value: XXh
7 0 PRPR3 PRPR2 PRPR1 PRPR0
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D7-D4. These bits are not used but have to be written to "0". PRPR3-PRPR0. These are the program ROM banking bits and the value loaded selects the corresponding page to be addressed in the lower part of 4K program address space as specified in Table 4. This register is undefined on reset. PRPR3 PRPR2 PRPR1 PRPR0 PC11 Memory Page Caution: This register contains at least one write Static Page X X X X 1 only bit. Single bit instructions (SET, RES, INC (Page 1) and DEC) should not be used. 0 0 0 0 0 Page 0 Note. Only the lower part of address space has Page 1 (Static 0 0 0 1 0 been bankswitched because interrupt vectors and Page) common subroutines should be available all the 0 0 1 0 0 Page 2 time. The reason of this structure is due to the fact 0 0 1 1 0 Page 3 that it is not possible to jump from a dynamic page 0 1 0 0 0 Page 4 to another, unless jumping back to the static page, 0 1 0 1 0 Page 5 changing contents of PRPR and then jumping to a 0 1 1 0 0 Page 6 different dynamic page. 0 1 1 1 0 Page 7 Care is required when handling the PRPR as it is .com 0 write only. For this reason, it is not allowed to 1 0 0 0 Page 8 change the PRPR contents while executing inter1 0 0 1 0 Page 9 rupts drivers, as the driver cannot save and than Table 4. Program Memory Map
Program Memory Page PAGE 0 Device Address 0000h-007Fh 0080h-07FFh 0800h-0F9Fh 0FA0h-0FEFh 0FF0h-0FF7h 0FF8h-0FFBh 0FFCh-0FFDh 0FFEh-0FFFh 0000h-000Fh 0010h-07FFh 0000h-000Fh 0010h-07FFh 0000h-000Fh 0010h-07FFh 0000h-000Fh 0010h-07FFh 0000h-000Fh 0010h-07FFh 0000h-000Fh 0010h-07FFh 0000h-000Fh 0010h-07FFh 0000h-000Fh 0010h-07FFh Description Reserved User ROM User ROM Reserved Interrupt Vectors Reserved NMI Vector Reset Vector Reserved User ROM Reserved User ROM (End of 8K ST6380, 81) Reserved User ROM Reserved User ROM Reserved User ROM Reserved User ROM (End of 16K ST6382, 83) Reserved User ROM Reserved User ROM (End of 20K ST6388, 89)
restore its previous content. Anyway, this operation may be necessary if the sum of common routines and interrupt drivers will take more than 2K bytes; in this case it could be necessary to divide the interrupt driver in a (minor) part in the static page (start and end), and in the second (major) part in one dynamic page. If it is impossible to avoid the writing of this register in interrupts drivers, an image of this register must be saved in a RAM location. Each time the program writes the PRPR register, the image register should also be written. The image register must be written first, so if an interrupt occurs between the two instructions the PRPR is not affected. Table 3. Program Memory Page Register coding
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PAGE 1 "STATIC"
PAGE 2 PAGE 3 PAGE 4 PAGE 5 PAGE 6 PAGE 7 PAGE 8 PAGE 9
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1.3.3 Data Space The ST6 Core instruction set operates on a specific space, referred to as the Data Space, which contains all the data necessary for the program. Figure 6. Data Space
DATA RAM/EEPROM/OSD BANK AREA DATA ROM WINDOW AREA X REGISTER Y REGISTER V REGISTER W REGISTER DATA RAM PORT A DATA REGISTER PORT B DATA REGISTER PORT C DATA REGISTER RESERVED PORT A DIRECTION REGISTER PORT B DIRECTION REGISTER PORT C DIRECTION REGISTER RESERVED INTERRUPT OPTION REGISTER DATA ROM WINDOW REGISTER PROGRAM ROM PAGE REGISTER RESERVED SPI DATA REGISTER PORT B OPTION REGISTER RESERVED ADC DATA REGISTER ADC CONTROL REGISTER TIMER 1 PRESCALER REGISTER TIMER 1 COUNTER REGISTER TIMER 1 STATUS/CONTROL REGISTER RESERVED WATCHDOG REGISTER 000h 03Fh 040h 07Fh 080h 081h 082h 083h 084h 0BFh 0C0h 0C1h 0C2h 0C3h 0C4h 0C5h 0C6h 0C7h 0C8h .com 0C9h 0CAh 0CBh 0CCh 0CDh 0CEh 0CFh 0D0h 0D1h 0D2h 0D3h 0D4h 0D5h 0D7h 0D8h OSD CONTROL REGISTERS LOCATED IN PAGE 5 OF BANKED DATA RAM VERTICAL START ADDRESS REGISTER HORIZONTAL START ADDRESS REGISTER VERTICAL SPACE REGISTER 0 HORIZONTAL SPACE REGISTER BACKGROUND COLOUR REGISTER VERTICAL SPACE REGISTER 1 OSD GLOBAL ENABLE REGISTER 038h 039h 03Ah 03Bh 03Ch 03Dh 03Fh ACCUMULATOR
The Data Space allows the addressing of RAM (256 bytes), EEPROM (384 bytes), ST6 Core and peripheral registers, as well as read-only data such as constants and look-up tables.
RESERVED TIMER 2 PRESCALER REGISTER TIMER 2 COUNTER REGISTER TIMER 2 STATUS/CONTROL REGISTER RESERVED MIRROR REGISTER XOR REGISTER DA 0 DATA/CONTROL REGISTER DA 1 DATA/CONTROL REGISTER DA 2 DATA/CONTROL REGISTER DA 3 DATA/CONTROL REGISTER IR & VSYNC STATUS REGISTER RESERVED DA 4 DATA/CONTROL REGISTER DA 5 DATA/CONTROL REGISTER DATA RAM BANK REGISTER DEDICATED LATCHES CONTROL REGISTER EEPROM CONTROL REGISTER SPI CONTROL REGISTER 1 SPI CONTROL REGISTER 2 OSD POLARITY SELECT REGISTER VS DATA REGISTER 1 VS DATA REGISTER 2 RESERVED 0D9h 0DAh 0DBh 0DCh 0DDh 0DEh 0DFh 0E0h 0E1h 0E2h 0E3h 0E4h 0E5h 0E6h 0E7h 0E8h 0E9h 0EAh 0EBh 0ECh 0EDh 0EEh 0EFh 0F0h 0F5h 0FEh 0FFh
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MEMORY SPACES (Cont'd) Data ROM Window Register (DRWR) Data ROM Addressing. All the read-only data are physically implemented in the ROM in which the Address: C9h - Write only Program Space is also implemented. The ROM Reset Value: XXh therefore contains the program to be executed and also the constants and the look-up tables needed 7 0 for the program. The locations of Data Space in DRWR DRWR DRWR DRWR DRWR DRWR DRWR DRWR which the different constants and look-up tables 7 6 5 4 3 2 1 0 are addressed by the ST6 Core can be considered as being a 64-byte window through which it is posDRWR7-DRWR0. These are the Data Rom Winsible to access to the read-only data stored in the dow bits that correspond to the upper bits of data ROM. This window is located from the 40h adROM program space. This register is undefined afdress to the 7Fh address in the Data space and alter reset. lows the direct reading of the bytes from the 000h address to the 03Fh address in the ROM. All the Caution: This register contains at least one write bytes of the ROM can be used to store either inonly bit. Single bit instructions (SET, RES, INC structions or read-only data. Indeed, the window and DEC) should not be used. can be moved by step of 64 bytes along the ROM Note: Care is required when handling the DRWR in writing the appropriate code in the Write-only as it is write only. For this reason, it is not allowed Data ROM Window register (DRWR, location C9h). The effective address of the byte to be read to change the DRWR contents while executing inas a data in the ROM is obtained by the concateterrupts drivers, as the driver cannot save and nation of the 6 less significant bits of the address in than restore its previous content. If it is impossible the Data Space (as less significant bits) and the to avoid the writing of this register in interrupts content of the DRWR (as most significant bits). So drivers, an image of this register must be saved in when addressing location 40h of data space, and a RAM location, and each time the program writes 0 is loaded in the DRWR, the physical addressed the DRWR it writes also the image register. The location in ROM is 00h. image register must be written first, so if an interNote: The data ROM Window can not address rupt occurs between the two instructions the window above the 16K byte range. DRWR register is not affected. .com Figure 7. Data ROM Window Memory Addressing
13 12 6 11 5 10 4 9 3 8 2 7 1 6 0 5 0 1 4 3 2 1 5 4 3 2 1 0 PROGRAM SPACE ADDRESS READ 0 DATA SPACE ADDRESS 40h-7Fh IN INSTRUCTION
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DATA ROM
WINDOW REGISTER 7 CONTENTS (DWR)
Example:
DWR=28h 0 0 1 0 1 0 0 0 0 1 0 1 1 0 0 1 DATA SPACE ADDRESS 59h
ROM ADDRESS:A19h
0
0
1
0
1
0
0
0
0
1
1
0
0
1
VR01573B
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ST6380, ST6381, ST6382, ST6383, ST6388, ST6389
MEMORY SPACES (Cont'd) 1.3.4 Data RAM/EEPROM/OSD RAM Addressing In all members of the ST638x family 64 bytes of data RAM are directly addressable in the data space from 80h to BFh addresses. The additional 192 bytes of RAM, the 384 bytes of EEPROM, and the OSD RAM can be addressed using the banks of 64 bytes located between addresses 00h and 3Fh. The selection of the bank is done by programming the Data RAM Bank Register (DRBR) located at the E8h address of the Data Space. In this way each bank of RAM, EEPROM or OSD RAM can select 64 bytes at a time. No more than one bank should be set at a time. Data RAM Bank Register (DRBR) Address: E8h - Write only Reset Value: XXh
7 0
Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used. Note: Care is required when handling the DRBR as it is write only. For this reason, it is not allowed to change the DRBR contents while executing interrupts drivers, as the driver cannot save and than restore its previous content. If it is impossible to avoid the writing of this register in interrupts drivers, an image of this register must be saved in a RAM location, and each time the program writes the DRBR it writes also the image register. The image register must be written first, so if an interrupt occurs between the two instructions the DRBR is not affected. Table 5. Data RAM Bank Register Set-up
Selection EEPROM Page 0 EEPROM Page 1 EEPROM Page 2 EEPROM Page 3 EEPROM Page 4 EEPROM Page 5 RAM Page 2 RAM Page 3 RAM Page 4 OSD Page 5
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DRBR Value Hex. Binary 01h 0000 0001 DRBR DRBR DRBR DRBR DRBR DRBR DRBR DRBR 7 6 5 4 3 2 1 0 02h 0000 0010 03h 0000 0011 DRBR7,DRBR1,DRBR0. These bits select the 81h 1000 0001 EEPROM pages. 82h 1000 0010 DRBR6, DRBR5. Each of these bits, when set, will 83h 1000 0011 select one OSD RAM register page. 04h 0000 0100 .com DRBR4,DRBR3,DRBR2. Each of these bits, when 08h 0000 1000 set, will select one RAM page. 10h 0001 0000 This register is undefined after reset. 20h 0010 0000
DataShee
Table 5 summarizes how to set the Data RAM Bank Register in order to select the various banks or pages.
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MEMORY SPACES (Cont'd) power consumption of the EEPROM is reduced to EEPROM Description the leakage values. The data space of ST638x family from 00h to 3Fh D5, D4. Reserved for testing purposes, they must is paged as described in Table 5. 384 bytes of be set to zero. EEPROM located in six pages of 64 bytes (pages 0,1,2,3,4 and 5, see Table 5). PS. WRITE ONLY. Once in Parallel Mode, as soon as the user software sets the PS bit the parThrough the programming of the Data RAM Bank allel writing of the 8 adjacent registers will start. PS Register (DRBR=E8h) the user can select the is internally reset at the end of the programming bank or page leaving unaffected the way to adprocedure. Note that less than 8 bytes can be writdress the static registers. The way to address the ten; after parallel programming the remaining un"dynamic" page is to set the DRBR as described in defined bytes will have no particular content. Table 5 (e.g. to select EEPROM page 0, the DRBR has to be loaded with content 01h, see PE. WRITE ONLY. This bit must be set by the user Data RAM/EEPROM/OSD RAM addressing for program in order to perform parallel programming additional information). Bits 0, 1 and 7 of the (more bytes per time). If PE is set and the "parallel DRBR are dedicated to the EEPROM. start bit" (PS) is low, up to 8 adjacent bytes can be written at the maximum speed, the content being The EEPROM pages do not require dedicated instored in volatile registers. These 8 adjacent bytes structions to be accessed in reading or writing. can be considered as row, whose A7, A6, A5, A4, The EEPROM is controlled by the EEPROM ConA3 are fixed while A2, A1 and A0 are the changing trol Register (EECR=EAh). Any EEPROM location bytes. PE is automatically reset at the end of any can be read just like any other data location, also parallel programming procedure. PE can be reset in terms of access time. by the user software before starting the programTo write an EEPROM location takes an average ming procedure, leaving unchanged the EEPROM time of 5 ms (10ms max) and during this time the registers. EEPROM is not accessible by the Core. A busy BS. READ ONLY. This bit will be automatically set flag can be read by the Core to know the EEPROM by the CORE when the user program modifies an status before trying any access. In writing the EEPROM EEPROM can work in two modes: Byte.com register. The user program has to test it Mode before any read or write EEPROM operation; any (BMODE) and Parallel Mode (PMODE). The attempt to access the EEPROM while "busy bit" is BMODE is the normal way to use the EEPROM set will be aborted and the writing procedure in and consists in accessing one byte at a time. The progress completed. PMODE consists in accessing 8 bytes per time. EN. WRITE ONLY. This bit MUST be set to one in EEPROM Control Register (EECR) order to write any EEPROM register. If the user Address: EAh - Read only/Write only program will attempt to write the EEPROM when Reset Value: EN= "0" the involved registers will be unaffected and the "busy bit" will not be set. 7 0 After RESET the content of EECR register will be SB PS PE BS EN 00h. Notes: When the EEPROM is busy (BS="1") the D7. Not used EECR can not be accessed in write mode, it is only possible to read BS status. This implies that as Caution: This register contains at least one write long as the EEPROM is busy it is not possible to only bit. Single bit instructions (SET, RES, INC change the status of the EEPROM control register. and DEC) should not be used. EECR bits 4 and 5 are reserved for test purposes, SB. WRITE ONLY. If this bit is set the EEPROM is and must never be set to "1". disabled (any access will be meaningless) and the
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MEMORY SPACES (Cont'd) Additional Notes on Parallel Mode. If the user wants to perform a parallel programming the first action should be the setting of the PE bit; from this moment, the first time the EEPROM will be addressed in writing, the ROW address will be latched and it will be possible to change it only at the end of the programming procedure or by resetting PE without programming the EEPROM. After the ROW address latching the Core can "see" just one EEPROM row (the selected one) and any attempt to write or read other rows will produce errors. Do not read the EEPROM while PE is set. As soon as PE bit is set, the 8 volatile ROW latches are cleared. From this moment the user can load data in the whole ROW or just in a subset. PS setting will modify the EEPROM registers corresponding to the ROW latches accessed after PE. For example, if the software sets PE and accesses EEPROM in writing at addresses 18h,1Ah,1Bh and then sets PS, these three registers will be modified at the same time; the remaining bytes will have no particular content. Note that PE is internally reset at the end of the programming procedure. This implies that the user must set PE bit between two parallel programming procedures. Anyway the user can set and then reset PE without performing any EEPROM programming. PS is a set only bit and is internally reset at the end of the programming procedure. Note that if the user tries to set PS while PE is not set there will not be any programming procedure and the PS bit will be unaffected. Consequently PS bit can not be set if EN is low. PS can be affected by the user set if, and only if, EN and PE bits are also set to one.
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2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION Indirect Registers (X, Y). These two indirect registers are used as pointers to memory locations in Data space. They are used in the register-indirect addressing mode. These registers can be addressed in the data space as RAM locations at addresses 80h (X) and 81h (Y). They can also be accessed with the direct, short direct, or bit direct addressing modes. Accordingly, the ST6 instruction set can use the indirect registers as any other register of the data space. Short Direct Registers (V, W). These two registers are used to save a byte in short direct addressing mode. They can be addressed in Data 2.2 CPU REGISTERS space as RAM locations at addresses 82h (V) and The ST6 Family CPU core features six registers 83h (W). They can also be accessed using the diand three pairs of flags available to the programrect and bit direct addressing modes. Thus, the mer. These are described in the following paraST6 instruction set can use the short direct regisgraphs. ters as any other register of the data space. Accumulator (A). The accumulator is an 8-bit Program Counter (PC). The program counter is a general purpose register used in all arithmetic cal12-bit register which contains the address of the culations, logical operations, and data manipulanext ROM location to be processed by the core. tions. The accumulator can be addressed in Data This ROM location may be an opcode, an operspace as a RAM location at address FFh. Thus the and, or the address of an operand. The 12-bit ST6 can manipulate the accumulator just like any length allows the direct addressing of 4096 bytes other register in Data space. in Program space. .com Figure 8. ST6 Core Block Diagram The CPU Core of ST6 devices is independent of the I/O or Memory configuration. As such, it may be thought of as an independent central processor communicating with on-chip I/O, Memory and Peripherals via internal address, data, and control buses. In-core communication is arranged as shown in Figure 8; the controller being externally linked to both the Reset and Oscillator circuits, while the core is linked to the dedicated on-chip peripherals via the serial data bus and indirectly, for interrupt purposes, through the control registers.
0,01 TO 8MHz RESET OSCin OSCout
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INTERRUPTS CONTROLLER DATA SPACE
OPCODE
FLAG VALUES
CONTROL SIGNALS 2 ADDRESS/READ LINE
DATA RAM/EEPROM
PROGRAM ROM/EPROM ADDRESS 256 DECODER A-DATA B-DATA
DATA ROM/EPROM
DEDICATIONS ACCUMULATOR
12
Program Counter and 6 LAYER STACK
FLAGS ALU RESULTS TO DATA SPACE (WRITE LINE) VR01811
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CPU REGISTERS (Cont'd) automatically selected after the reset of the MCU, However, if the program space contains more than the ST6 core uses at first the NMI flags. 4096 bytes, the additional memory in program space can be addressed by using the Program Stack. The ST6 CPU includes a true LIFO hardBank Switch register. ware stack which eliminates the need for a stack pointer. The stack consists of six separate 12-bit The PC value is incremented after reading the adRAM locations that do not belong to the data dress of the current instruction. To execute relative space RAM area. When a subroutine call (or interjumps, the PC and the offset are shifted through rupt request) occurs, the contents of each level are the ALU, where they are added; the result is then shifted into the next higher level, while the content shifted back into the PC. The program counter can of the PC is shifted into the first level (the original be changed in the following ways: contents of the sixth stack level are lost). When a - JP (Jump) instruction . . . . . PC=Jump address subroutine or interrupt return occurs (RET or RETI - CALL instruction . . . . . . . . . PC= Call address instructions), the first level register is shifted back into the PC and the value of each level is popped - Relative Branch Instruction . PC= PC +/- offset back into the previous level. Since the accumula- Interrupt . . . . . . . . . . . . . .PC=Interrupt vector tor, in common with all other data space registers, is not stored in this stack, management of these - Reset . . . . . . . . . . . . . . . . . PC= Reset vector registers should be performed within the subrou- RET & RETI instructions . . . . PC= Pop (stack) tine. The stack will remain in its "deepest" position if more than 6 nested calls or interrupts are execut- Normal instruction . . . . . . . . . . . . . PC= PC + 1 ed, and consequently the last return address will Flags (C, Z). The ST6 CPU includes three pairs of be lost. It will also remain in its highest position if flags (Carry and Zero), each pair being associated the stack is empty and a RET or RETI is executed. with one of the three normal modes of operation: In this case the next instruction will be executed. Normal mode, Interrupt mode and Non Maskable Interrupt mode. Each pair consists of a CARRY Figure 9. ST6 CPU Programming Mode flag and a ZERO flag. One pair (CN, ZN) is used during Normal operation, another pair is used during Interrupt mode (CI, ZI), and a third pair is used b7 X REG. POINTER b0 INDEX SHORT in the Non Maskable Interrupt mode (CNMI, ZN.com REGISTER DIRECT b7 Y REG. POINTER b0 MI). ADDRESSING MODE The ST6 CPU uses the pair of flags associated V REGISTER b7 b0 with the current mode: as soon as an interrupt (or b7 W REGISTER b0 a Non Maskable Interrupt) is generated, the ST6 CPU uses the Interrupt flags (resp. the NMI flags) b0 b7 ACCUM ULATOR instead of the Normal flags. When the RETI instruction is executed, the previously used set of PROGRAM COUNTER b11 b0 flags is restored. It should be noted that each flag set can only be addressed in its own context (Non Maskable Interrupt, Normal Interrupt or Main routine). The flags are not cleared during context SIX LEVELS switching and thus retain their status. STACK REGISTER The Carry flag is set when a carry or a borrow occurs during arithmetic operations; otherwise it is cleared. The Carry flag is also set to the value of the bit tested in a bit test instruction; it also participates in the rotate left instruction. NORMAL FLAGS C Z The Zero flag is set if the result of the last arithmeC Z INTERRUPT FLAGS tic or logical operation was equal to zero; otherwise it is cleared. NMI FLAGS C Z Switching between the three sets of flags is performed automatically when an NMI, an interrupt or VA000423 a RETI instructions occurs. As the NMI mode is
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3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES
3.1 ON-CHIP CLOCK OSCILLATOR Figure 10. Clock Generator Option 1 The internal oscillator circuit is designed to require a minimum of external components. A crystal quartz, a ceramic resonator, or an external signal CRYSTAL/RESONATOR CLOCK (provided to the OSCin pin) may be used to generate a system clock with various stability/cost tradeoffs. The typical clock frequency is 8MHz. Please ST6xxx note that different frequencies will affect the operation of those peripherals (D/As, SPI) whose reference frequencies are derived from the system OSCin OSCout clock. The different clock generator connection schemes are shown in Figure 10 and 11. One machine cycle takes 13 oscillator pulses; 12 clock pulses are needed to increment the PC while and additional CL1 CL2 13th pulse is needed to stabilize the internal latchVA0016B es during memory addressing. This means that with a clock frequency of 8MHz the machine cycle is 1.625Sec. Figure 11. Clock Generator Option 2 The crystal oscillator start-up time is a function of many variables: crystal parameters (especially RS), oscillator load capacitance (CL), IC parameEXTERNAL CLOCK ters, ambient temperature, and supply voltage.It must be observed that the crystal or ceramic leads and circuit connections must be as short as possiST6xxx ble. Typical values for CL1 and CL2 are in the range of 15pF to 22pF but these should be chosen .com OSCin OSCout based on the crystal manufacturers specification. Typical input capacitance for OSCin and OSCout pins is 5pF. NC The oscillator output frequency is internally divided VA0015C by 13 to produce the machine cycle and by 12 to produce the Timers and the Watchdog clock. A byte cycle is the smallest unit needed to execute Figure 12. OSCin, OSCout Diagram any operation (i.e., increment the program counter). An instruction may need two, four, or five byte cycles to be executed (See Table 6). OSCin, OSCout (QUARTZ PINS) Table 6. Instruction Timing with 8MHz Clock
Instruction Type Branch if set/reset Branch & Subroutine Branch Bit Manipulation Load Instruction Arithmetic & Logic Conditional Branch Program Control Cycles 5 4 4 4 4 2 2 Cycles Cycles Cycles Cycles Cycles Cycles Cycles Execution Time 8.125s 6.50s 6.50s 6.50s 6.50s 3.25s 3.25s
VDD OSCin
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1M
VDD OSCout
VA00462
In
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3.2 RESETS The MCU can be reset in three ways: Figure 13). The circuit guarantees that the MCU will exit or enter the reset state correctly, without - by the external Reset input being pulled low; spurious effects, ensuring, for example, that EEP- by Power-on Reset; ROM contents are not corrupted. - by the digital Watchdog peripheral timing out. Figure 13. Power ON/OFF Reset operation 3.2.1 RESET Input The RESET pin may be connected to a device of the application board in order to reset the MCU if VDD required. The RESET pin may be pulled low in 4.2 RUN, WAIT or STOP mode. This input can be Threshold used to reset the MCU internal state and ensure a 3.4 correct start-up procedure. The pin is active low and features a Schmitt trigger input. The internal Reset signal is generated by adding a delay to the t external signal. Therefore even short pulses on the RESET pin are acceptable, provided VDD has completed its rising phase and that the oscillator is running correctly (normal RUN or WAIT modes). The MCU is kept in the Reset state as long as the VDD RESET pin is held low. POWER ON/OFF If RESET activation occurs in RUN or WAIT modes, processing of the user program is stopped (RUN mode only), the Inputs and Outputs are conRESET figured as inputs with pull-up resistors if available. When the level on the RESET pin then goes high, the initialization sequence is executed following t VR02037 expiry of the internal delay period. .com Figure 14. Reset and Interrupt Processing If RESET pin activation occurs in the STOP mode, the oscillator starts up and all Inputs and Outputs RESET are configured as inputs with pull-up resistors if available. When the level of the RESET pin then goes high, the initialization sequence is executed NMI MASK SET following expiry of the internal delay period. INT LATCH CLEARED ( IF PRESENT ) 3.2.2 Power-on Reset The function of the POR circuit consists in waking SELECT up the MCU at an appropriate stage during the NMI MODE FLAGS power-on sequence. At the beginning of this sequence, the MCU is configured in the Reset state: all I/O ports are configured as inputs with pull-up PUT FFEH ON ADDRESS BUS resistors and no instruction is executed. When the power supply voltage rises to a sufficient level, the oscillator starts to operate, whereupon an internal delay is initiated, in order to allow the oscillator to YES IS RESET STILL fully stabilize before executing the first instruction. PRESENT? The initialization sequence is executed immediately following the internal delay. NO The internal delay is generated by an on-chip LOAD PC counter. The internal reset line is released 2048 inFROM RESET LOCATIONS FFE/FFF ternal clock cycles after release of the external reset. The internal POR device is a static mechanism FETCH INSTRUCTION which forces the reset state when V DD is below a VA000427 threshold voltage in the range 3.4 to 4.2 Volts (see
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RESETS (Cont'd) 3.2.3 Watchdog Reset The MCU provides a Watchdog timer function in order to ensure graceful recovery from software upsets. If the Watchdog register is not refreshed before an end-of-count condition is reached, the internal reset will be activated. This, amongst other things, resets the watchdog counter. The MCU restarts just as though the Reset had been generated by the RESET pin, including the built-in stabilisation delay period. 3.2.4 Application Note No external resistor is required between VDD and the Reset pin, thanks to the built-in pull-up device. 3.2.5 MCU Initialization Sequence When a reset occurs the stack is reset, the PC is loaded with the address of the Reset Vector (located in program ROM starting at address 0FFEh). A jump to the beginning of the user program must be coded at this address. Following a Reset, the Interrupt flag is automatically set, so that the CPU is in Non Maskable Interrupt mode; this prevents the initialisation routine from being interrupted. The initialisation routine should therefore be terminated by a RETI instruction, in order to revert to normal mode and enable interrupts. If no pending interrupt is present at the end of the initialisation routine, the MCU will continue by processing the instruction immediately following the RETI instruction. If, however, a pending interrupt is present, it will be serviced. Figure 15. Reset and Interrupt Processing
RESET
JP RESET VECTOR
JP:2 BYTES/4 CYCLES
INITIALIZATION ROUTINE RETI
RETI: 1 BYTE/2 CYCLES
VA00181
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Figure 16. Reset Circuit
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OSCILLATOR SIGNAL COUNTER RESET (ACTIVE LOW) 1k VDD 300k WATCHDOG RESET POWER ON/OFF RESET TO ST6 RESET
ST6 INTERNAL RESET
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3.3 POWER SAVING MODES mode) before the start of the WAIT sequence, but STOP and WAIT modes have been implemented also of the type of the interrupt request that is genin the ST638x in order to reduce the current conerated. In all cases the GEN bit of IOR has to be sumption of the device during idle periods. These set to 1 in order to restart from WAIT mode. Contwo modes are described in the following paratrary to the operation of NMI in the run mode, the graphs. Since the hardware activated digital NMI is masked in WAIT mode if GEN=0. watchdog function is present, the STOP instruction is de-activated and any attempt to execute it Normal Mode. If the MCU Core was in the main will cause the automatic execution of a WAIT inroutine when the WAIT instruction has been exestruction. cuted, the Core exits from WAIT mode as soon as an interrupt occurs; the corresponding interrupt 3.3.1 WAIT Mode routine is executed, and at the end of the interrupt The configuration of the MCU in the WAIT mode service routine, the instruction that follows the occurs as soon as the WAIT instruction is executWAIT instruction is executed if no other interrupts ed. The microcontroller can also be considered as are pending. being in a "software frozen" state where the Core Non-maskable Interrupt Mode. If the WAIT instops processing the instructions of the routine, struction has been executed during the execution the contents of the RAM locations and peripheral of the non-maskable interrupt routine, the MCU registers are saved as long as the power supply Core outputs from WAIT mode as soon as any involtage is higher than the RAM retention voltage terrupt occurs: the instruction that follows the but where the peripherals are still working. The WAIT instruction is executed and the MCU Core is WAIT mode is used when the user wants to restill in the non-maskable interrupt mode even if anduce the consumption of the MCU when it is in other interrupt has been generated. idle, while not losing count of time or monitoring of external events. The oscillator is not stopped in orNormal Interrupt Mode. If the MCU Core was in der to provide clock signal to the peripherals. The the interrupt mode before the initialization of the timers counting may be enabled (writing the PSI WAIT sequence, it outputs from the wait mode as bit in TSCR1 register) and the timer interrupt may soon as any interrupt occurs. Nevertheless, two be also enabled before entering the WAIT mode; cases have to be considered: this allows the WAIT mode to be left when timer in- If the terrupt occurs. If the exit from the WAIT mode is .com interrupt is a normal interrupt, the interrupt routine in which the WAIT was entered will be performed with a general RESET (either from the completed with the execution of the instruction activation of the external pin or by watchdog reset) that follows the WAIT and the MCU Core is still in the MCU will enter a normal reset procedure as the interrupt mode. At the end of this routine described in the RESET chapter. If an interrupt is generated during WAIT mode the MCU behaviour pending interrupts will be serviced in accordance depends on the state of the MCU Core before the to their priority. initialization of the WAIT sequence, but also of the - If the interrupt is a non-maskable interrupt, the kind of the interrupt request that is generated. This non-maskable routine is processed at first. Then, case will be described in the following paragraphs. the routine in which the WAIT was entered will be In any case, the MCU Core does not generate any completed with the execution of the instruction delay after the occurrence of the interrupt because that follows the WAIT and the MCU Core is still in the oscillator clock is still available. the normal interrupt mode. 3.3.2 STOP Mode Notes: Since the hardware activated watchdog is present If all the interrupt sources are disabled, the restart on the ST638x, the STOP instruction has been deof the MCU can only be done by a Reset activaactivated. Any attempt to execute a STOP instruction. The Wait instruction is not executed if an ention will cause a WAIT instruction to be executed abled interrupt request is pending. In ST638x deinstead. vices, the hardware activated digital watchdog 3.3.3 Exit from WAIT Mode function is present. As the watchdog is always acThe following paragraphs describe the output protivated, the STOP instruction is de-activated and cedure of the MCU Core from WAIT mode when any attempt to execute the STOP instruction will an interrupt occurs. It must be noted that the recause an execution of a WAIT instruction. start sequence depends on the original state of the MCU (normal, interrupt or non-maskable interrupt
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3.4 HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION The hardware activated digital watchdog function consists of a down counter that is automatically initialized after reset so that this function does not need to be activated by the user program. As the watchdog function is always activated this down counter can not be used as a timer. The watchdog is using one data space register (HWDR location D8h). The watchdog register is set to FEh on reset and immediately starts to count down, requiring no software start. Similarly the hardware activated watchdog can not be stopped or delayed by software. The watchdog time can be programmed using the 6 MSBs in the watchdog register, this gives the possibility to generate a reset in a time between 3072 to 196608 oscillator cycles in 64 possible steps. (With a clock frequency of 8MHz this means from 384ms to 24.576ms). The reset is prevented if the register is reloaded with the desired value before bits 2-7 decrement from all zeros to all ones. The presence of the hardware watchdog deactivates the STOP instruction and a WAIT instruction is automatically executed instead of a STOP. Bit 1 of the watchdog register (set to one at reset) can be used to generate a software reset if cleared to zero). Figure 17 shows the watchdog block diagram while Figure 18 shows its working principle.
Figure 17. Hardware Activated Watchdog Block Diagram
RESET
Q RSFF R S
-2
7
DB1.7 LOAD SET
-2 8 SET
-12
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DB0
8
WRITE RESET DATA BUS
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HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION (Cont'd) Figure 18. Hardware Activated Watchdog Hardware Activated Watchdog Register (HWDR) Working Principle Address: D8h - Read/Write Reset Value: 0FEh
D0
7 T1 T2 T3 T4 T5 T6 SR 0 C
BIT7
D1 WATCHDOG CONTROL REGISTER
BIT6
T1-T6. These are the watchdog counter bits. It should be noted that D7 (T1) is the LSB of the counter and D2 (T6) is the MSB of the counter, these bits are in the opposite order to normal. SR. This bit is set to one during the reset phase and will generate a software reset if cleared to zero. C. This is the watchdog activation bit that is hardware set. The watchdog function is always activated independently of changes of value of this bit. The register reset value is FEh (Bit 1-7 set to one, Bit 0 cleared).
D2
BIT5
RESET
D3
BIT4
D4
BIT3
D5
BIT2
D6
BIT1
D7
BIT0
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8-BIT
DOWN COUNTER
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OSC-12
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3.5 INTERRUPT The ST638x Core can manage 4 different maska3.5.1 Interrupt Vectors/Sources ble interrupt sources, plus one non-maskable inThe ST638x Core includes 5 different interrupt terrupt source (top priority level interrupt). Each vectors in order to branch to 5 different interrupt source is associated with a particular interrupt vecroutines. The interrupt vectors are located in the tor that contains a Jump instruction to the related fixed (or static) page of the Program Space. interrupt service routine. Each vector is located in The interrupt vector associated with the nonthe Program Space at a particular address (see maskable interrupt source is named interrupt vecTable 7). When a source provides an interrupt retor #0. It is located at the (FFCh,FFDh) addresses quest, and the request processing is also enabled in the Program Space. This vector is associated by the ST638x Core, then the PC register is loadwith the PC6/IRIN pin. ed with the address of the interrupt vector (i.e. of the Jump instruction). Finally, the PC is loaded The interrupt vectors located at addresses (FF6h, with the address of the Jump instruction and the FF7h), (FF4h, FF5h), (FF2h, FF3h), (FF0h, FF1h) interrupt routine is processed. are named interrupt vectors #1, #2, #3 and #4 respectively. These vectors are associated with TIMThe relationship between vector and source and ER 2 (#1), VSYNC (#2), TIMER 1 (#3), the associated priority is hardware fixed for the difPC4(PWRIN) (#4) and ADC (#4). ferent ST638x devices. For some interrupt sources it is also possible to select by software the kind Table 7. Interrupt Vectors/Sources of event that will generate the interrupt. Relationships All interrupts can be disabled by writing to the GEN Associated Vector bit (global interrupt enable) of the interrupt option Interrupt Source Vector Address register (address C8h). After a reset, ST638x is in non maskable interrupt mode, so no interrupts will Interrupt 0FFCh-0FFDh PC6/IRIN Pin 1 be accepted and NMI flags will be used, until a Vector # 0 (NMI) RETI instruction is executed. If an interrupt is exeInterrupt Timer 2 0FF6h-0FF7h cuted, one special cycle is made by the core, durVector # 1 ing that the PC is set to the related interrupt.com vector Interrupt Vsync 0FF4h-0FF5h address. A jump instruction at this address has to Vector #2 redirect program execution to the beginning of the Interrupt related interrupt routine. The interrupt detecting Timer 1 0FF2h-0FF3h Vector #3 cycle, also resets the related interrupt flag (not Interrupt available to the user), so that another interrupt can PC4/PWRIN, ADC 0FF0h-0FF1h Vector #4 be stored for this current vector, while its driver is under execution. Note 1. This pin is associated with the NMI InterIf additional interrupts arrive from the same rupt Vector source, they will be lost. NMI can interrupt other in3.5.2 Interrupt Priority terrupt routines at any time, while other interrupts cannot interrupt each other. If more than one interThe non-maskable interrupt request has the highrupt is waiting for service, they are executed acest priority and can interrupt any other interrupt cording to their priority. The lower the number, the routines at any time, nevertheless the other interhigher the priority. Priority is, therefore, fixed. Inrupts cannot interrupt each other. If more than one terrupts are checked during the last cycle of an ininterrupt request is pending, they are processed struction (RETI included). Level sensitive interby the ST638x Core according to their priority levrupts have to be valid during this period. el: vector #1 has the higher priority while vector #4 the lower. The priority of each interrupt source is hardware fixed.
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INTERRUPTS (Cont'd) 3.5.3 Interrupt Option Register Interrupt Option Register (IOR) Address: (C8h) - Write only Reset Value: X000XXXXb
7 0
EL1
ES2
GEN
-
-
-
-
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The Interrupt Option Register (IOR register, location C8h) is used to enable/disable the individual interrupt sources and to select the operating mode of the external interrupt inputs. This register can be addressed in the Data Space as RAM location at the C8h address, nevertheless it is a write-only register that can not be accessed with single-bit operations. The operating modes of the external interrupt inputs associated to interrupt vectors #1 and #2 are selected through bits 5 and 6 of the IOR register. Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used. D7. Not used. EL1. This is the Edge/Level selection bit of interrupt #1. When set to one, the interrupt is generatFigure 19. Interrupt Processing Flow-Chart ed on low level of the related signal; when cleared .com to zero, the interrupt is generated on falling edge. INSTRUCTION The bit is cleared to zero after reset. ES2. This is the edge selection bit on interrupt #2. FETCH This bit is used on the ST638x devices with onINSTRUCTION chip OSD generator for VSYNC detection. When this bit is se to one, the interrupt #2 is positive EXECUTE edge sensitive, when cleared to zero the negative INSTRUCTION edge sensitive interrupt is selected. GEN. This is the global enable bit. When set to LOAD PC FROM NO INTERRUPT VECTOR WAS one all interrupts are globally enabled; when this (FFC/FFD) THE INSTRUCTION A RETI ? bit is cleared to zero all interrupts are disabled (excluding NMI). YES SET IS THE CORE YES D3 - D0. These bits are not used. ALREADY IN INTERRUPT MASK ? NORMAL MODE? 3.5.4 Interrupt Procedure NO The interrupt procedure is very similar to a call proCLEAR PUSH THE INTERRUPT MASK PC INTO THE STACK cedure; the user can consider the interrupt as an asynchronous call procedure. As this is an asynchronous event the user does not know about the SELECT PROGRAM FLAGS SELECT context and the time at which it occurred. As a result INTERNAL MODE FLAG the user should save all the data space registers which will be used inside the interrupt routines. "POP" THE STACKED PC There are separate sets of processor flags for normal, interrupt and non-maskable interrupt modes which are automatically switched and so these do CHECK IF THERE IS NO AN INTERRUPT REQUEST ? not need to be saved. AND INTERRUPT MASK
YES
VA000014
The following list summarizes the interrupt procedure (refer also to Figure 19*) - Interrupt detection - The flags C and Z of the main routine are exchanged with the flags C and Z of the interrupt routine (resp. the NMI flags) - The value of the PC is stored in the first level of the stack - The normal interrupt lines are inhibited (NMI still active) - The edge flip-flop is reset - The related interrupt vector is loaded in the PC. - User selected registers are saved inside the interrupt service routine (normally on a software stack) - The source of the interrupt is found by polling (if more than one source is associated to the same vector) - Interrupt servicing - Return from interrupt (RETI) - Automatically the ST638x core switches back to the normal flags (resp the interrupt flags) and pops the previous PC value from the stack
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INTERRUPTS (Cont'd) The interrupt routine begins usually by the identifilatched signal is to service the interrupt. Care must cation of the device that has generated the interbe taken not to generate spurious interrupts. This rupt request. The user should save the registers interrupt may be used to synchronize the VSYNC which are used inside the interrupt routine (that signal in order to change characters in the OSD holds relevant data) into a software stack. After the only when the screen is on vertical blanking (if deRETI instruction execution, the Core carries out sired). This method may also be used to blink the previous actions and the main routine can concharacters. tinue. TIMER 1 Interrupt (#3). The TIMER 1 Interrupt is 3.5.5 ST638x Interrupt Details connected to the fourth interrupt #3 (0FF2h) which detects a low level (latched in the timer). IR Interrupt (#0). The IRIN/PC6 Interrupt is connected to the first interrupt #0 (NMI, 0FFCh). If the PWR and ADC Interrupt (#4). The PWR and AnIRINT interrupt is disabled at the Latch circuitry, alog to Digital Converter Interrupts are connected then it will be high. The #0 interrupt input detects a by a logical AND to the fifth interrupt #4 (0FF0h). If high to low level. Note that once #0 has been the PWRINT is disabled at the PWR circuitry, then latched, then the only way to remove the latched it will be high. The #4 interrupt input detects a low #0 signal is to service the interrupt. #0 can interlevel. A simple latch is provided from the PC4 rupt the other interrupts. A simple latch is provided (PWRIN) pin in order to generate the PWRINT sigfrom the PC6(IRIN) pin in order to generate the IRnal. This latch can be triggered by either the posiINT signal. This latch can be triggered by either tive or negative edge of the PWRIN signal. the positive or negative edge of IRINT signal. IRPWRINT is inverted with respect to the latch. The INT is inverted with respect to the latch. The latch latch can be reset by software. can be read by software and reset by software. Notes: Global disable does not reset edge sensiTIMER 2 Interrupt (#1). The TIMER 2 Interrupt is tive interrupt flags. These edge sensitive interrupts connected to the interrupt #1 (0FF6h). The TIMER become pending again when global disabling is re2 interrupt generates a low level (which is latched leased. Moreover, edge sensitive interrupts are in the timer). Only the low level selection for #1 can stored in the related flags also when interrupts are be used. Bit 6 of the interrupt option register C8h globally .com disabled, unless each edge sensitive inhas to be set. terrupt is also individually disabled before the interrupting event happens. Global disable is done VSYNC Interrupt (#2). The VSYNC Interrupt is by clearing the GEN bit of Interrupt option register, connected to the interrupt #2. When disabled the while any individual disable is done in the control VSYNC INT signal is low. The VSYNC INT signal register of the peripheral. The on-chip Timer peis inverted with respect to the signal applied to the ripherals have an interrupt request flag bit (TMZ), VSYNC pin. Bit 5 of the interrupt option register this bit is set to one when the device wants to genC8h is used to select the negative edge (ES2=0) erate an interrupt request and a mask bit (ETI) that or the positive edge (ES2=1); the edge will depend must be set to one to allow the transfer of the flag on the application. Note that once an edge has bit to the Core. been latched, then the only way to remove the
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Figure 20. Interrupt circuit diagram
VDD
DLCR Bit 2
FF CLK Q CLR FF CLK Q CLR INT #0 - NMI (FFC,D)
PC6/IRIN
DLCR Bit 1
DLCR Bit 3
I0 Start
T IM E R 2 TSCR2 B it 6
FF CLK Q CLR I1 Start
0 MUX 1 IOR Bit 6 RESTART FROM STOP/WAIT INT #1 (FF6,7)
VDD NPVIR Bit 6 VSYNC IOR Bit 5 FF CLK Q CLR I2 Start INT #3 (FF2,3) INT #2 (FF4,5)
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VDD
TIMER 1 TSCR1 Bit 6
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ADC ADCR Bit 7
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PC4/PWRIN
FF CLK Q CLR
INT #4 (FF0,1)
DLCR Bit 5
IOR Bit 4 : GEN
DLCR Bit 4
DLCR Bit 6
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4 ON-CHIP PERIPHERALS
4.1 I/O PORTS and Direction registers are associated with the PA0 The ST638x microcontrollers use three standard I/ line of Port A). O ports (A,B,C) with up to eight pins on each port; refer to the device pin configurations to see which There are three Data registers (DRA, DRB, DRC), pins are available. that are used to read the voltage level values of the lines programmed in the input mode, or to write the Each line can be individually programmed either in logic value of the signal to be output on the lines conthe input mode or the output mode as follows by figured in the output mode. The port Data Registers software. can be read to get the effective logic levels of the - Output pins, but they can be also written by the user soft- Input with on-chip pull-up resistor (selected by ware, in conjunction with the related Data Direction software) Register and the Option Register (Port B only), to select the different input mode options. Single-bit - Input without on-chip pull-up resistor (selected operations on I/O registers (bit set/reset instrucby software) tions) are possible but care is necessary because - Analog inputs (PB0-PB6) reading in input mode is made from I/O pins and therefore might be influenced by the external load, Note: pins with 12V open-drain capability do not while writing will directly affect the Port data register have pull-up resistors. causing an undesired changes of the input configIn output mode the following hardware configurauration. The three Data Direction registers (DDRA, tions are available: DDRB, DDRC) allow the selection of the direction of each pin (input or output). - Open-drain output 12V (PA4-PA7, PC4-PC7) All the I/O registers can be read or written as any - Open-drain output 5V (PC0-PC3, PB0-PB6) other RAM location of the data space, so no extra - Push-pull output (PA0-PA3, PB0-PB6) RAM cell is needed for port data storing and manipulation. During the initialization of the MCU, all The lines are organized in three ports (port A,B,C). the I/O registers are cleared and the input mode with The ports occupy 7 registers in the data space. .com is selected on all the pins thus avoiding pin pull-up Each bit of these registers is associated with a parconflicts (with the exception of PC2 that is set in outticular line (for instance, the bits 0 of the Port A Data put mode and is set high i.e. high impedance).
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I/O PORTS (Cont'd) 4.1.1 Details of I/O Ports When programmed as an input a pull-up resistor (if available) can be switched active under program control. When programmed as an output the I/O port will operate either in the push-pull mode or the open-drain mode according to the hardware fixed configuration as specified below. Port A. PA0-PA3 are available as push-pull when outputs. PA4-PA7 are available as open-drain (no push-pull programmability) capable of withstanding 12V (no resistive pull-up in input mode). PA6PA7 has been specially designed for higher driving capability and are able to sink 25mA with a maximum VOL of 1V. Port B. All lines are available as open drain, pushpull when outputs or analog input. Port C. PC0-PC3 are available as open-drain capable of withstanding a maximum VDD+0.3V. PC4-PC7 are avail-able as open-drain capable of withstanding 12V (no resistive pull-up in input mode). Some lines are also used as I/O buffers for signals coming from the on-chip SPI. Table 8. I/O Port Options Selection (Port A)
DDR 0 0 1 DR 0 1 X Mode Input Input Output Option With on-chip pull-up resistor .com pull-up resistor Without on-chip Output open-drain or push-pull
In this case the final signal on the output pin is equivalent to a wired AND with the programmed data output. If the user needs to use the serial peripheral, the I/ O line should be set in output mode while the open-drain configuration is hardware fixed; the corresponding data bit must set to one. If the latched interrupt functions are used (IRIN, PWRIN) then the corresponding pins should be set to input mode. On ST638x the I/O pins with double or special functions are: - PC0/SCL (connected to the SPI clock signal) - PC1/SDA (connected to the SPI data signal) - PC3/SEN (connected to the SPI enable signal) - PC4/PWRIN (connected to the PWRIN interrupt latch) - PC6/IRIN (connected to the IRIN interrupt latch) All the Port A,B and C I/O lines have Schmitt-trigger input configuration with a typical hysteresis of 1V.
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Note X: Means don't care. Table 9. I/O Port Options Selection (Port B)
DDR 0 0 0 1 1 OR 0 0 1 0 1 DR 0 1 1 x X Mode Input Input Input Output Output Option With on-chip pull-up resistor Without on-chip pull-up resistor Analog input Open-drain output Push-pull output
Note X: Means don't care.
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I/O PORTS (Cont'd) Table 10. I/O Port Option
MODE AVAILABLE ON(1)
VDD
SCHEMATIC
PA0-PA3 Input PB0-PB6 PC0-PC3 Data in
VDD
Input with pull up
PA0-PA3 PB0-PB6 PC0-PC3 Data in
VDD
Analog input
PB0-PB6 ADC
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Open drain output 5mA/5V Open drain output 5mA / 12V Open drain output 25mA/12V
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PC0-PC3 PA4-PA5 PB0-PB6 PC4-PC7 PA6-PA7 Data out
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VDD
Push-pull output 5mA Push-pull output 10mA
PB0-PB6 PA0-PA3
VDD
Data out
Note 1. Provided the correct configuration has been selected.
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I/O PORTS (Cont'd) 4.1.2 I/O Pin Programming Each pin can be individually programmed as input or output with different input and output configurations. This is achieved by writing to the relevant bit in the data (DR) and data direction register (DDR). Table 11 shows all the port configurations that can be selected by the user software. 4.1.3 Input/Output Configurations The Table 9 shows the I/O lines hardware configuration for the different options. Notes: The WAIT instruction allows the ST638x to be used in situations where low power consumption is needed. This can only be achieved however if the I/O pins either are programmed as inputs with well defined logic levels or have no power consuming resistive loads in output mode. As the same die is used for the different ST638x versions the unavailable I/O lines of ST638x should be programmed in output mode. Single-bit operations on I/O registers are possible but care is necessary because reading in input mode is made from I/O pins while writing will directly affect the Port data register causing an undesired changes of the input configuration. PA7-PA0. These are the I/O port A data bits. Reset at power-on. PB6-PB0. These are the I/O port B data bits. Reset at power-on. PC7-PC0. Set to 04h at power-on. Bit 2 (PC2 pin) is set to one (open drain therefore high impedance). 4.1.4.2 Data Direction Registers Port A, B, C Data Direction Register Address: C4h (PA), C5h (PB), C6h (PC) - Read/ Write Reset value:00h
7 PA/ PC7 PA/ PB/ PC6 PA/ PB/ PC5 PA/ PB/ PC4 PA/ PB/ PC3 PA/ PB/ PC2 PA/ PB/ PC1 0 PA/ PB/ PC0
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PA7-PA0. These are the I/O port A data direction bits. When a bit is cleared to zero the related I/O line is in input mode, if bit is set to one the related I/O line is in output mode. Reset at power-on. PB6-PB0. These are the I/O port B data direction bits. When a bit is cleared to zero the related I/O line is in input mode, if bit is set to one the related Table 11. I/O Port Options Selection (Port C) I/O line is in output mode. Reset at power-on. DDR DR Mode Option PC7-PC0. These are the I/O port C data direction .com 0 0 Input With on-chip pull-up resistor bits. When a bit is cleared to zero the related I/O line is in input mode, if bit is set to one the related 0 1 Input Without on-chip pull-up resistor I/O line is in output mode. Set to 04h at power-on. 1 X Output Open-drain Bit 2 (PC2 pin) is set to one (output mode selectNote: X. Means don't care. ed). 4.1.4 I/O Port Registers 4.1.4.3 Data Direction Registers 4.1.4.1 Data Registers Port B Option Register Ports A, B, C Data Register Address: CDh - Read/Write Address: C0h (PA), C1h (PB), C2h (PC) - Read/ Reset value:00h Write Reset Value: 00h 7 0
7 PA/ PC7 PA/ PB/ PC6 PA/ PB/ PC5 PA/ PB/ PC4 PA/ PB/ PC3 PA/ PB/ PC2 PA/ PB/ PC1 0 PA/ PB/ PC0 PB6 PB5 PB4 PB3 PB2 PB1 PB0
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PB6-PB0. These are the I/O port B data direction bits. If bit is set to one the related I/O line is in analog input mode. Reset at power-on.
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4.2 TIMERS The ST638x devices offer two on-chip Timer peripherals consisting of an 8-bit counter with a 7-bit programmable prescaler, thus giving a maximum count of 215, and a control logic that allows configuration the peripheral operating mode. Figure 21 shows the Timer block diagram. The content of the 8-bit counters can be read/written in the Timer/ Counter registers TCR that are addressed in the data space as RAM locations at addresses D3h (Timer 1), DBh (Timer 2). The state of the 7-bit prescaler can be read in the PSC register at addresses D2h (Timer 1) and DAh (Timer 2). The control logic is managed by TSCR registers at D4h (Timer 1) and DCh (Timer 2) addresses as described in the following paragraphs. The following description applies to all Timers. The 8-bit counter is decrement by the output (rising edge) coming from the 7-bit prescaler and can be loaded and read under program control. When it decrements to zero then the TMZ (timer zero) bit in the TSCR is set to one. If the ETI (enable timer interrupt) bit in the TSCR is also set to one an interrupt request, associated to interrupt vector #3 for Timer 1 and #1 for Timer 2, is generated. The interrupt of the timer can be used to exit the MCU from the WAIT mode. Figure 21. Timer Peripheral Block Diagram The prescaler decrements on rising edge. The prescaler input is the oscillator frequency divided by 12. Depending on the division factor programmed by PS2/PS1/PS0 (see Table 12) bits in the TSCR, the clock input of the timer/counter register is multiplexed to different sources. On division factor 1, the clock input of the prescaler is also that of timer/counter; on factor 2, bit 0 of prescaler register is connected to the clock input of TCR. This bit changes its state with the half frequency of prescaler clock input. On factor 4, bit 1 of PSC is connected to clock input of TCR, and so on. On division factor 128, the MSB bit 6 of PSC is connected to clock input of TCR. The prescaler initialize bit (PSI) in the TSCR register must be set to one to allow the prescaler (and hence the counter) to start. If it is cleared to zero then all of the prescaler bits are set to one and the counter is inhibited from counting.The prescaler can be given any value between 0 and 7Fh by writing to the related register address, if bit PSI in the TSCR register is set to one. The tap of the prescaler is selected using the PS2/PS1/PS0 bits in the control register. Figure 22 illustrates the Timer working principle.
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8 6 5 4 3 2 1 0
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DATABUS 8 8 8-BIT COUNTER
b7 b6 b5 b4
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8
b3 b2 b1 b0
PSC
SELECT 1 OF 8
STATUS/CONTROL REGISTER
TMZ ETI TOUT DOUT PSI PS2 PS1 PS0
3
TIMER INTERRUPT LINE SYNCHRONIZATION LOGIC LATCH
fOSC
:12
VA00009
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ST6380, ST6381, ST6382, ST6383, ST6388, ST6389
TIMERS (Cont'd) 4.2.1 Timer Operating Modes Since in the ST638x devices the external TIMER pin is not connected, the only allowed operating mode is the output mode, which is selected by setting bit 4 and by clearing bit 5 in the TSCR1 register. This procedure will enable Timer 1 and Timer 2. Output Mode (TSCR1 D4 = 1, TSCR1 D5 = 0). On this mode the timer prescaler is clocked by the prescaler clock input (OSC/12). The user can select the desired prescaler division ratio through the PS2/PS1/PS0 bits. When TCR count reaches 0, it sets the TMZ bit in the TSCR. The TMZ bit can be tested under program control to perform timer functions whenever it goes high. Bits D4 and D5 on TSCR2 (Timer 2) register are not implemented. Timer Interrupt When the counter register decrements to zero and the software controlled ETI (enable timer interrupt) bit is set to one then an interrupt request associated to interrupt vector #3 (for Timer 1), to interrupt Figure 22. Timer Working Principle
7-BIT PRESCALER
vector #1 (for Timer 2) is generated. When the counter decrements to zero also the TMZ bit in the TSCR register is set to one. Notes: TMZ is set when the counter reaches 00h; however, it may be set by writing 00h in the TCR register or setting the bit 7 of the TSCR register. TMZ bit must be cleared by user software when servicing the timer interrupt to avoid undesired interrupts when leaving the interrupt service routine. After reset, the 8-bit counter register is loaded to FFh while the 7-bit prescaler is loaded to 7Fh, and the TSCR register is cleared which means that timer is stopped (PSI=0) and timer interrupt disabled. A write to the TCR register will predominate over the 8-bit counter decrement to 00h function, i.e. if a write and a TCR register decrement to 00h occur simultaneously, the write will take precedence, and the TMZ bit is not set until the 8-bit counter reaches 00h again. The values of the TCR and the PSC registers can be read accurately at any time.
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CLOCK
BIT0
BIT1
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BIT5
BIT6
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0
1
2
4 3 8-1 MULTIPLEXER
5
6
7
PS0 PS1 PS2
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
8-BIT COUNTER
VA00186
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ST6380, ST6381, ST6382, ST6383, ST6388, ST6389
TIMERS (Cont'd) 4.2.2 Timer Status Control Registers (TSCR) Timers 1 and 2 Address: D4h (Timer 1), DCh (Timer 2) - Read/ Write Reset Value: 00h
7 TMZ ETI D5 D4 PSI PS2 PS1 0 PS0
The TSCR1 and TSCR2 registers are cleared on reset. The correct D4-D5 combination must be written in TSCR1 by user's software to enable the operation of Timer 1 and 2. Table 12. Prescaler Division Factors
PS2 0 0 0 0 1 1 1 1 PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 Divided By 1 2 4 8 16 32 64 128
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TMZ. Low-to-high transition indicates that the timer count register has decremented to zero. This bit must be cleared by user software before to start with a new count. ETI. This bit, when set, enables the timer interrupt (vector #3 for Timer 1, vector #2 for Timer 2 request). If ETI=0 the timer interrupt is disabled. If ETI= 1 and TMZ= 1 an interrupt request is gener4.2.3 Timer Counter Registers (TCR) ated. Timer Counter 1 and 2 D5. This is the timers enable bit D5. It must be Address: D3h (Timer Counter 1), DBh (Timer cleared to 0 together with a set to 1 of bit D4 to enCounter 2) - Read/Write able Timer 1 and Timer 2 functions. It is not implemented on registers TSCR2. Reset Value: FFh D4. This is the timers enable bit D4. This bit must 7 0 be set to 1 together with a clear to 0 of bit D5 to enable all Timers (Timer 1 and 2) functions. It is not D7 D6 D5 D4 D3 D2 D1 D0 implemented on registers TSCR2. .com D5 D4 Timers Bit 7-0 = D7-D0: Counter Bits.
0 0 1 0 1 X Disabled Enabled Reserved
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PSI. Used to initialize the prescaler and inhibit its counting while PSI = 0 the prescaler is set to 7Fh and the counter is inhibited. When PSI = 1 the prescaler is enabled to count downwards. As long as PSI= 0 both counter and prescaler are not running. PS2-PS0. These bits select the division ratio of the prescaler register. (see Table 12)
4.2.4 Timer Prescaler Registers (PSCR) Timer Prescalers 1 and 2 Address: D2h (Timer Prescaler 1), DAh (Timer Prescaler 2) - Read/Write Reset Value: 7Fh
7 D7 D6 D5 D4 D3 D2 D1 0 D0
Bit 7 = D7: Always read as "0". Bit 6-0 = D6-D0: Prescaler Bits.
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4.3 SERIAL PERIPHERAL INTERFACE The ST638x Serial Peripheral Interface (SPI) has - On S-BUS by a transition of the SEN line (1 to 0 been designed to be cost effective and flexible in Start, 0 to 1 Stop) while the SCL line is at high interfacing the various peripherals in TV applicalevel. tions. - On I2C BUS by a transition of the SDA line (10 It maintains the software flexibility but adds hardStart, 01Stop) while the SCL line is at high level. ware configurations suitable to drive devices Start and Stop condition are always generated by which require a fast exchange of data. The three the master (ST638x SPI can only work as single pins dedicated for serial data transfer (single masmaster). The bus is busy after the start condition ter only) can operate in the following ways: and can be considered again free only when a cer- as standard I/O lines (software configuration) tain time delay is left after the stop condition. In the S-BUS configuration the SDA line is only allowed 2C BUS (two pins) - as S-BUS or as I to change during the time SCL line is low. After the - as standard (shift register) SPI start information the SEN line returns to high level and remains unchanged for all the data transmisWhen using the hardware SPI, a fixed clock rate of sion time. When the transmission is completed the 62.5kHz is provided. It has to be noted that the first SDA line is set to high level and, at the same time, bit that is output on the data line by the 8-bit shift the SEN line returns to the low level in order to register is the MSB. supply the stop information with a low to high tran2 4.3.1 S-BUS/I C BUS Protocol Information sition, while the SCL line is at high level. On the SThe S-BUS is a three-wire bidirectional data-bus BUS, as on the I2C BUS, each eight bit information with functional features similar to the I2C BUS. In (byte) is followed by one acknowledged bit which fact the S-BUS includes decoding of Start/Stop is a high level put on the SDA line by the transmitconditions and the arbitration procedure in case of ter. A peripheral that acknowledges has to pull multimaster system configuration (the ST638x SPI down the SDA line during the acknowledge clock allows a single-master only operation). The SDA pulse. An addressed receiver has to generate an line, in the I2C BUS represents the AND combinaacknowledge after the reception of each byte; othtion of SDA and SEN lines in the S-BUS. If the erwise .com the SDA line remains at the high level durSDA and the SEN lines are short-circuit connecting the ninth clock pulse time. In this case the mased, they appear as the SDA line of the I 2C BUS. ter transmitter can generate the Stop condition, via The Start/Stop conditions are detected (by the exthe SEN (or SDA in I2C BUS) line, in order to abort 2 ternal peripherals suited to work with S-BUS/I C the transfer. BUS) in the following way:
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SERIAL PERIPHERAL INTERFACE (Cont'd) a. an optional data byte to address (if needed) the Start/Stop Acknowledge. The timing specs of the slave location to be written (it can be a word S-BUS protocol require that data on the SDA (only address in a memory or a register address, on this line for I2C BUS) and SEN lines be stable during the "high" time of SCL. Two exceptions to etc.). this rule are foreseen and they are used to signal b. a "data" byte which will be written at the the start and stop condition of data transfer. address given in the previous byte. - On S-BUS by a transition of the SEN line (10 c. further data bytes. Start, 01 Stop) while the SCL line is at high level. d. a STOP condition - On I 2C BUS by a transition of the SDA line (10 A data transfer is always terminated by a stop conStart, 01 Stop) while the SCL line is at high level. dition generated from the master. The ST638x peData are transmitted in 8-bit groups; after each ripheral must finish with a stop condition before group, a ninth bit is interposed, with the purpose of another start is given. Figure 23 shows an examacknowledging the transmitting sequence (the ple of write operation. transmit device place a "1" on the bus, the ac2. R/W = "1" (Read) knowledging receiver a "0"). In this case the slave acts as transmitter and, Interface Protocol. This paragraph deals with the therefore, the transmission direction is changed. In description of data protocol structure. The interread mode two different conditions can be considface protocol includes: ered: - A start condition a. The master reads slave immediately after first - A "slave chip address" byte, transmitted by the byte. In this case after the slave address sent master, containing two different information: from the master with read condition enabled the a. the code identifying the device the master master transmitter becomes master receiver wants to address (this information is present in and the slave receiver becomes slave transmitthe first seven bits) ter. b. the direction of transmission on the bus (this b. The master reads a specified register or loca.com information is given in the 8th bit of the byte); tion of the slave. In this case the first sent byte "0" means "Write", that is from the master to the will contain the slave address with write condislave, while "1" means "Read". The addressed tion enabled, then the second byte will specify slave must always acknowledge. the address of the register to be read. At this moment a new start is given together with the The sequence from, now on, is different according slave address in read mode and the procedure to the value of R/W bit. will proceed as described in previous point "a". 1. R/W = "0" (Write) In all the following bytes the master acts as transmitter; the sequence follows with:
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SERIAL PERIPHERAL INTERFACE (Cont'd) Figure 23. IC Master Transmit to Slave Receiver (Write Mode)
ACKNOWLEDGE FROM SLAVE ACKNOWLEDGE FROM SLAVE MSB S SLAVE ADDRESS O A WORD ADDRESS A DATA A P ACKNOWLEDGE FROM SLAVE
START
R/W
STOP
Figure 24. IC Master Reads Slave Immediately After First Byte (Read Mode)
ACKNOWLEDGE FROM SLAVE MSB S SLAVE ADDRESS 1 A DATA A ACKNOWLEDGE FROM MASTER MSB DATA 1 P NO ACKNOWLEDGE FROM MASTER
START
R/W
n BYTES
STOP
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.com Figure 25. IC Master Reads After Setting Slave Register Address (Write Address, Read Data)
ACKNOWLEDGE FROM SLAVE ACKNOWLEDGE FROM SLAVE
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S
SLAVE ADDRESS
0
A
X
WORD ADDRESS
A
P
START
R/W
STOP
ACKNOWLEDGE FROM SLAVE MSB S SLAVE ADDRESS 1 A DATA
ACKNOWLEDGE FROM MASTER MSB A DATA
NO ACKNOWLEDGE FROM MASTER
1
P
START
R/W
STOP
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SERIAL PERIPHERAL INTERFACE (Cont'd) 4.3.2 S-BUS/I2C BUS Timing Diagrams The clock of the S-BUS/I2C BUS of the ST638x SPI (single master only) has a fixed bus clock frequency of 62.5KHz. All the devices connected to the bus must be able to follow transfers with freFigure 26. S-BUS Timing Diagram
SCL 0 1 1 2 3 4 5 6 7 A
quencies up to 62.5KHz, either by being able to transmit or receive at that speed or by applying the clock synchronization procedure which will force the master into a wait state and stretch low periods.
SEN (TRANSMIT)
SDA (TRANSMIT)
^^^ SDA pulled low by receiver if acknowledged.
SEN (RECEIVE)
SDA (RECEIVE)
^^^ SDA pulled low by SPI Peripheral.
SCL 0 1 1 2 3 4 5 6 7 A
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SEN (START)
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SDA (START)
^^^ SDA pulled low by receiver if acknowledged.
SCL 0 1 1 2 3 4 5 6 7 A
SEN (STOP)
SDA (STOP) SDA pulled low by receiver if acknowledge. If in receive then there will be no ACK. by the SPI.
^^^
VA00454
Note: The third pin, SEN, should be high; it is not used in the S-BUS SDA and SEN.)
I2C
BUS. Logically SDA is the AND of the
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SERIAL PERIPHERAL INTERFACE (Cont'd) Figure 27. I2C BUS Timing Diagram
SCL
0 1 2 3 4 5 6 7 A
SDA (TRANSMIT) SDA pulled low by receiver if acknowledged.
SDA (RECEIVE) SDA pulled low by SPI Peripheral.
SCL
0 1 2 3 5 6 7 A
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SDA (START)
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SDA pulled low by receiver if acknowledged.
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SCL
0 1 2 3 4 5 6 7 A
SDA (STOP) SDA pulled low by receiver if acknowledge. If in receive then there will be no ACK. by the SPI.
VA00455
Note: The third pin, SEN, should be high; it is not used in the I2C BUS. Logically SDA is the AND of the S-BUS SDA and SEN.)
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SERIAL PERIPHERAL INTERFACE (Cont'd) 4.3.3 Compatibility S-BUS/I 2C BUS Using the S-BUS protocol it is possible to implement mixed system including S-BUS/I 2C BUS bus peripherals. In order to have the compatibility with the I 2C BUS peripherals, the devices including the S-BUS interface must have their SDA and SEN pins connected together as shown in the following Figure 28. S-BUS/ I2C BUS Mixed Configurations Figure 28 (a and b). It is also possible to use mixed S-BUS/I2C BUS protocols as showed in Figure 28 (c). S-BUS peripherals will only react to S-BUS protocol signals, while I2C BUS peripherals will only react to I2C BUS signals. Multimaster configuration is not possible with the ST63xx SPI (single master only).
SCL SDA SEN
SCL SDA SEN
SCL SDA SEN
SCL SDA SEN
ST6 S-BUS PROTOCOL SCL SDA I2C-BUS SLAVE
ST6 I2C-BUS PROTOCOL SCL SDA I2C-BUS SLAVE
VA00457
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SCL SDA SEN SCL SDA SEN
VA00456
b
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ST6 S-BUS/I2C-BUS PROTOCOL SCL SDA I2C-BUS SLAVE
VA00452
c
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SERIAL PERIPHERAL INTERFACE (Cont'd) 4.3.4 STD SPI Protocol (Shift Register) This protocol is similar to the I2C BUS with the exception that there is no acknowledge pulse and there are no stop or start bits. The clock cannot be slowed down by the external peripherals. In this case all three outputs should be high in order not to lock the software I/Os from functioning. SPI Standard Bus Protocol: The standard bus protocol is selected by loading the SPI Control Register 1 (SCR1 Add. EBh). Bit 0 named I2C must be set at one and bit 1 named STD must be reset. When the standard bus protocol is selected bit 2 of the SCR1 is meaningless. This bit named STOP bit is used only in I2C BUS or SBUS. However take care that THE STOP BIT MUST BE RESET WHEN THE STANDARD PROTOCOL IS USED. This bit is set to ZERO after RESET.
Figure 29. Software Bus (Hardware Bus Disabled) Timing Diagram
CLOCK (was SCL) 0 1 2 3 4 5 6 7
IDENT (was SEN, this is optionally controlled by software; output as far as hardware is concerned is high).
DATA (was SDA, TRANSMIT)
DATA (was SDA, RECEIVE)
VA00453
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4.3.5 SPI Data/Control Register For I/O details on SCL (Serial Clock), SDA (Serial Data) and SEN (Serial Enable) please refer to I/O Ports description with reference to the following registers: Port C data register, Address C2h (Read/Write). - BIT D0 "SCL" - BIT D1 "SDA" - BIT D3 "SEN" Port C data direction register, Address C6h (Read/ Write).
SPI Serial Data Register (SSDR) Address: CCh - Read/Write Reset Value: XXh
7 0
SSDR SSDR SSDR SSDR SSDR SSDR SSDR SSDR 7 6 5 4 3 2 1 0
SSDR7-0. These are the SPI data bits. They can be neither read nor written when SPI is operating (BUSY bit set). They are undefined after reset.
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SERIAL PERIPHERAL INTERFACE (Cont'd) SPI Control Register 1 (SCR1) Address: EBh - Write only Reset Value: 00h
7 STR STP STD/ SPI 0 S-BUS/ 2 I CBUS
SPI Control Register 2 (SCR2) Address: ECh - Read/Write Reset Value: 00h
7 TX/RX VRY/S ACN 0 BSY
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Caution: This register contains at least one write Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC only bit. Single bit instructions (SET, RES, INC and DEC) should not be used. and DEC) should not be used. b7-b4. These bits are not used. b7-b4. These bits are not used. 2 TX/RX. Write Only. When this bit is set, current STR. This is Start bit for I C BUS/S-BUS. This bit byte operation is a transmission. When it is reset, is meaningless when STD/SPI enable bit is current operation is a reception. Set to zero after cleared to zero. If this bit is set to one and STD/SPI bit is also set to "1" then SPI Start generation, bereset. fore beginning of transmission, is enabled. Set to VRY/S. Read Only/Write Only. This bit has two difzero after reset. ferent functions in relation to read or write operaSTP. This is Stop bit for I2C BUS/S-BUS. This bit tion. Reading Operation: when STD and/or TRX is meaningless when STD/SPI enable bit is bits is cleared to 0, this bit is meaningless. When cleared to zero. If this bit is set to one and STD/SPI bits STD and TX are set to 1, this bit is set each bit is also set to "1" then SPI Stop condition genertime BSY bit is set. This bit is reset during byte opation is enabled. STP bit must be reset when eration if real data on SDA line are different from standard protocol is used (this is also the default the output from the shift register. Set to zero after reset conditions). Set to zero after reset. reset. Writing Operation: it enables (if set to one) STD, SPI Enable. This bit, in conjunction with Sor disables (if cleared to zero) the interrupt coming BUS/I2C BUS bit, allows the SPI disable and will .com from VSYNC pin. Undefined after reset. Refer to 2 select between I C BUS/S-BUS and Standard OSD description for additional information. shift register protocols. If this bit is set to one, it se2C BUS and S-BUS protocols; final seACN. Read Only. If STD bit (D1 of SCR1 register) lects both I is cleared to zero this bit is meaningless. When lection between them is made by S-BUS/I2C BUS STD is set to one, this bit is set to one if no Acbit. If this bit is cleared to zero when S-BUS/I2C BUS is set to "1" the Standard shift register protoknowledge has been received. In this case it is aucol is selected. If this bit is cleared to "0" when Stomatically reset when BSY is set again. Set to BUS/I2C BUS is cleared to 0 the SPI is disabled. zero after reset. Set to zero after reset. BSY. Read/Set Only. This is the busy bit. When a S-BUS/I2C BUS Selection. This bit, in conjunction one is loaded into this bit the SPI interface start the with STD/SPI bit, allows the SPI disable and will transmission of the data byte loaded into SSDR 2 select between I C BUS and S-BUS protocols. If data register or receiving and building the receive this bit is cleared to "0" when STD bit is also "0", data into the SSDR data register. This is done in the SPI interface is disabled. If this bit is cleared to accordance with the protocol, direction and start/ zero when STD bit is set to "1", the I2C BUS protostop condition(s). This bit is automatically cleared col will be selected. If this bit is set to "1" when at the end of the current byte operation. Cleared to STD bit is set to "1", the S-BUS protocol will be sezero after reset. lected. Cleared to zero after reset. Note: The SPI shift register is also the data transTable 13. SPI Mode Selection mission register and the data received register; this feature is made possible by using the serial D1 D0 SPI Function 2 structure of the ST638x and thus reducing size STD/SP S-BUS/I C BUS and complexity.
0 0 1 1 0 1 0 1 Disabled STD Shift Reg. I2C BUS S-BUS
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SERIAL PERIPHERAL INTERFACE (Cont'd) During transmission or reception of data, all access to serial data register is therefore disabled. The reception or transmission of data is started by setting the BUSY bit to "1"; this will be automatically reset at the end of the operation. After reset, the busy bit is cleared to "0", and the hardware SPI disabled by clearing bit 0 and bit 1 of SPI control register 1 to "0". The outputs from the hardware SPI are "ANDed" to the standard I/O software controlled outputs. If the hardware SPI is in operation the Port C pins related to the SPI should be configured as outputs using the Data Direction Register and should be set high. When the SPI is configured as the S-BUS, the three pins PC0, PC1 and PC3 become the pins SCL, SDA and SEN respectively. When configured as the I2C BUS the pins PC0 and PC1 are configured as the pins SCL and SDA; PC3 is not driven and can be used as a general purpose I/O pin. In the case of the STD SPI the pins PC0 and PC1 become the signals CLOCK and DATA, PC3 is not driven and can be used as general purpose I/O pin. The VERIFY bit is available when the SPI is configured as either S-BUS or I2C BUS. At the start of a byte transmission, the verify bit is set to one. If at any time during the transmission of the following eight bits, the data on the SDA line does not match the data forced by the SPI (while SCL is high), then the VERIFY bit is reset. The verify is available only during transmission for the S-BUS and I2C BUS; for other protocol it is not defined. The SDA and SCL signal entering the SPI are buffered in order to remove any minor glitches. When STD bit is set to one (S-BUS or I2C BUS selected), and TRX bit is reset (receiving data), and STOP bit is set (last byte of current communication), the SPI interface does not generate the Acknowledge, according to S-BUS/I2C BUS specifications. PCO-SCL, PC1-SDA and PC3SEN lines are standard drive I/O port pins with open-drain output configuration (maximum voltage that can be applied to these pins is VDD+ 0.3V).
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4.4 14-BIT VOLTAGE SYNTHESIS TUNING PERIPHERAL The ST638x on-chip voltage synthesis tuning peTable 14. . Fine Tuning Pulse Addition ripheral has been integrated to allow the generaN of pulses added at the tion of tuning reference voltage in low/mid end TV Fine Tuning following cycles set applications. The peripheral is composed of a (7 LSB) (0... 127) 14-bit counter that allows the conversion of the 0000001 64 digital content in a tuning voltage, available at the VS output pin, by using Pulse Width Modification 0000010 32, 96 (PWM), and Bit Rate Multiplier (BRM) techniques. 0000100 16, 48, 80, 112 The 14-bit counter gives 16384 steps which allows 0001000 8, 24,....104, 120 a resolution of approximately 2mV over a tuning 0010000 4, 12,....116, 124 voltage of 32V; this corresponds to a tuning reso0100000 2, 6,.....122, 126 lution of about 40KHz per step in the UHF band 1000000 1, 3,.....125, 127 (the actual value will depend on the characteristics of the tuner). The VS output pin has a standard drive push-pull The tuning word consists of a 14-bit word conoutput configuration. tained in the registers VSDATA1 (location 0EEh) and VSDATA2 (location 0EFh). Coarse tuning 4.4.2 VS Tuning Cell Registers (PWM) is performed using the seven MSBits, Voltage Synthesis Data Register 1 (VSDR1) while fine tuning (BRM) is performed using the Address: EEh - Write only data in the seven LSBits. With all zeros loaded the output is zero; as the tuning voltage increases Reset Value: XXh from all zeros, the number of pulses in one period 7 0 increase to 128 with all pulses being the same width. For values larger than 128, the PWM takes VSDR1 VSDR1 VSDR1 VSDR1 VSDR1 VSDR1 VSDR1 VSDR1 over and the number of pulses in one period re7 6 5 4 3 2 1 0 mains constant at 128, but the width changes. At the other end of the scale, when almost all ones Caution: This register contains at least one write .com Single bit instructions (SET, RES, INC are loaded, the pulses will start to link together and only bit. the number of pulses will decrease. When all ones and DEC) should not be used. are loaded, the output will be almost 100% high D7-D0. These are the 8 least significant VS data but will have a low pulse (1/16384 of the high bits. Bit 0 is the LSB. This register is undefined on pulse). reset. 4.4.1 Output Details Inside the on-chip Voltage Synthesis are included Voltage Synthesis Data Register 2 (VSDR2) the register latches, a reference counter, PWM Address: EFh - Write only and BRM control circuitry. In the ST638x the clock Reset Value: XXh for the 14-bit reference counter is 4MHz derived from the 8MHz system clock. From the circuit point 7 0 of view, the seven most significant bits control the coarse tuning, while the seven least significant bits VSDR2 VSDR2 VSDR2 VSDR2 VSDR2 VSDR2 5 4 3 2 1 0 control the fine tuning. From the application and software point of view, the 14 bits can be considCaution: This register contains at least one write ered as one binary number. only bit. Single bit instructions (SET, RES, INC As already mentioned the coarse tuning consists and DEC) should not be used. of a PWM signal with 128 steps; we can consider D7-D6. These bits are not used. the fine tuning to cover 128 coarse tuning cycles. The addition of pulses is described in the following D5-D0. These are the 6 most significant VS data Table. bits. Bit 5 is the MSB. This register is undefined on reset.
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4.5 6-BIT PWM D/A CONVERTERS The D/A macrocell contains up to six PWM D/A outputs (31.25kHz repetition, DA0-DA5) with six bit resolution. Each D/A converter of ST638x is composed by the following main blocks: - pre-divider - 6-bit counter - data latches and compare circuits The pre-divider uses the clock input frequency (8MHz typical) and its output clocks the 6-bit freerunning counter. The data latched in the six registers (E0h, E1h, E2h, E3h, E6h and E7h) control the six D/A outputs (DA0,1,2, 3, 4 and 5). When all zeros are loaded the relevant output is an high logic level; all 1's correspond to a pulse with a 1/64 duty cycle and almost 100% zero level. The repetition frequency is 31.25kHz and is related to the 8MHz clock frequency. Use of a different oscillator frequency will result in a different repetition frequency. All D/A outputs are open-drain with standard current drive capability and able to withstand up to 12V. DA0-DA5 Data/Control Register (DADCR) Address: E0h, E1h, E2h, E3h, E6h, E7h, - Write only Reset Value: XXh
7 0 DADCR DADCR DADCR DADCR DADCR DADCR 5 4 3 2 1 0
Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used. DADCR0-DADCR5. These are the 6 bits of the PWM digital to analog converter. Undefined after reset. Figure 30. 6-bit PWM D/A Output Configuration
DA0-DA5 OUT (OPEN-DRAIN, 12V) Out
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4.6 A/D CONVERTER (ADC) This action is also needed before entering WAIT The A/D converter peripheral is an 8-bit analog to mode, since the A/D comparator is not automatidigital converter with analog inputs as alternate I/O cally disabled in WAIT mode. functions (the number of which is device dependent), offering 8-bit resolution with a typical converDuring Reset, any conversion in progress is sion time of 70us (at an oscillator clock frequency stopped, the control register is reset to 40h and the of 8MHz). ADC interrupt is masked (EAI=0). The ADC converts the input voltage by a process Figure 31. ADC Block Diagram of successive approximations, using a clock frequency derived from the oscillator with a division factor of twelve. With an oscillator clock frequency less than 1.2MHz, conversion accuracy is deINTERRUPT creased. CLOCK Ain CONVERTER RESET Selection of the input pin is done by configuring AVSS the related I/O line as an analog input via the OpAVDD tion and Data registers (refer to I/O ports description for additional information). Only one I/O line must be configured as an analog input at any time. The user must avoid any situation in which more CONTROL REGISTER RESULT REGISTER than one I/O pin is selected as an analog input simultaneously, to avoid device malfunction. 8 8 The ADC uses two registers in the data space: the ADC data conversion register, ADR, which stores CORE CORE the conversion result, and the ADC control regisCONTROL SIGNALS VA00418 ter, ADCR, used to program the ADC functions. A conversion is started by writing a "1" to the Start bit (STA) in the ADC control register. This auto4.6.1 Application Notes matically clears (resets to "0") the End Of Conversion Bit (EOC). When a conversion is complete, The A/D .com converter does not feature a sample and the EOC bit is automatically set to "1", in order to hold circuit. The analog voltage to be measured flag that conversion is complete and that the data should therefore be stable during the entire conin the ADC data conversion register is valid. Each version cycle. Voltage variation should not exceed conversion has to be separately initiated by writing 1/2 LSB for the optimum conversion accuracy. A to the STA bit. low pass filter may be used at the analog input pins to reduce input voltage variation during conThe STA bit is continuously scanned so that, if the version. user sets it to "1" while a previous conversion is in progress, a new conversion is started before comWhen selected as an analog channel, the input pin pleting the previous one. The start bit (STA) is a is internally connected to a capacitor Cad of typiwrite only bit, any attempt to read it will show a logcally 12pF. For maximum accuracy, this capacitor ical "0". must be fully charged at the beginning of conversion. In the worst case, conversion starts one inThe A/D converter features a maskable interrupt struction (6.5 s) after the channel has been seassociated with the end of conversion. This interlected. In worst case conditions, the impedance, rupt is associated with interrupt vector #4 and ocASI, of the analog voltage source is calculated uscurs when the EOC bit is set (i.e. when a convering the following formula: sion is completed). The interrupt is masked using the EAI (interrupt mask) bit in the control register. 6.5s = 9 x Cad x ASI The power consumption of the device can be re(capacitor charged to over 99.9%), i.e. 30 k induced by turning off the ADC peripheral. This is cluding a 50% guardband. ASI can be higher if Cad done by setting the PDS bit in the ADC control reghas been charged for a longer period by adding inister to "0". If PDS="1", the A/D is powered and enstructions before the start of conversion (adding abled for conversion. This bit must be set at least more than 26 CPU cycles is pointless). one instruction before the beginning of the conversion to allow stabilisation of the A/D converter.
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A/D CONVERTER (Cont'd) Since the ADC is on the same chip as the microprocessor, the user should not switch heavily loaded output signals during conversion, if high precision is required. Such switching will affect the supply voltages used as analog references. The accuracy of the conversion depends on the quality of the power supplies (V DD and VSS). The user must take special care to ensure a well regulated reference voltage is present on the VDD and VSS pins (power supply voltage variations must be less than 5V/ms). This implies, in particular, that a suitable decoupling capacitor is used at the VDD pin. The converter resolution is given by: be working and the resulting noise could affect conversion accuracy. A/D Converter Control Register (ADCR) Address: 0D1h -- Read/Write, Write only Reset value: 40h
7 EAI EOC STA PDS 0 -
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Bit 7 = EAI: Enable A/D Interrupt. If this bit is set to "1" the A/D interrupt (vector #4) is enabled, when EAI=0 the interrupt is disabled. Bit 6 = EOC: End of conversion. Read Only. This read only bit indicates when a conversion has V DD - V SS been completed. This bit is automatically reset to --------------------------"0" when the STA bit is written. If the user is using 256 the interrupt option then this bit can be used as an interrupt pending bit. Data in the data conversion register are valid only when this bit is set to "1". The Input voltage (Ain) which is to be converted Bit 5 = STA: Start of Conversion. Write Only. Writmust be constant for 1s before conversion and ing a "1" to this bit will start a conversion on the seremain constant during conversion. lected channel and automatically reset to "0" the Conversion resolution can be improved if the powEOC bit. If the bit is set again when a conversion is er supply voltage (VDD) to the microcontroller is in progress, the present conversion is stopped and lowered. a new one will take place. This bit is write only, any In order to optimise conversion resolution, the user attempt to read it will show a logical zero. can configure the microcontroller in WAIT .com mode, Bit 4 = PDS: Power Down Selection. This bit actibecause this mode minimises noise disturbances vates the A/D converter if set to "1". Writing a "0" to and power supply variations due to output switchthis bit will put the ADC in power down mode (idle ing. Nevertheless, the WAIT instruction should be mode). executed as soon as possible after the beginning Bit 3-0 = Not used of the conversion, because execution of the WAIT instruction may cause a small variation of the VDD Caution: This register contains at least one write voltage. The negative effect of this variation is minonly bit. Single bit instructions (SET, RES, INC imized at the beginning of the conversion when the and DEC) should not be used. converter is less sensitive, rather than at the end A/D Converter Data Register (ADR) of conversion, when the less significant bits are determined. Address: 0D0h -- Read only The best configuration, from an accuracy standReset value: XXh point, is WAIT mode with the Timer stopped. In7 0 deed, only the ADC peripheral and the oscillator are then still working. The MCU must be woken up D7 D6 D5 D4 D3 D2 D1 D0 from WAIT mode by the ADC interrupt at the end of the conversion. It should be noted that waking up the microcontroller could also be done using Bit 7-0 = D7-D0: 8 Bit A/D Conversion Result. the Timer interrupt, but in this case the Timer will
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4.7 DEDICATED LATCHES Two latches are available which may generate inDedicated Latches Control Register (DLCR) terrupts to the ST638x core. The IR latch is set eiAddress: E9h - Write only ther by the falling or rising edge of the signal on pin Reset Value: XXh PC6(IRIN). If bit 1 (IRPOSEDGE) of the latches register (E9h) is high, then the latch will be trig7 0 gered on the rising edge of the signal at IRRESP- PWRINT- PWRED RESIR- IRINTPC6(IRIN). If bit 1 (IRPOSEDGE) is low, then the POSED WRLAT EN GE LAT EN latch will be triggered on the falling edge of the sigGE nal at PC6(IRIN). The IR latch can be reset by setting bit 3 (RESIRLAT) of the latches register; the Caution: This register contains at least one write bit is write only and a high should be written every only bit. Single bit instructions (SET, RES, INC time the IR latch needs to be reset. If bit 2 (IRINTand DEC) should not be used. EN) of the latches register (E9h) is high, then the Bit 7. This bit is not used output of the IR latch, IRINTN, may generate an inRESPWRLAT. Resets the PWR latch; this bit is terrupt (#0). IRINTN is inverted with respect to the write only. state of the IR latch. If bit 2 (IRINTEN) is low, then the output of the IR latch, IRINTN, is forced PWRINTEN. This bit enables the PWRINT signal high.The state of the IR latch may be read from bit (#4) from the latch to the ST638x core. Undefined 3 (IRLATCH) of register E4h; if the IR latch is set, after reset. then bit 3 will be high. The PWR latch is set either PWREDGE. The bit determines the edge which by the falling or rising edge of the signal on pin will cause the PWRIN latch to be set. If this bit is PC4(PWRIN). If bit 4 (PWREDGE) of the latches high, than the PWRIN latch will be set on the rising register (E9h) is high, then the latch will be trigedge of the PWRIN signal. Undefined after reset. gered on the rising edge of the signal at RESIRLAT. Resets the IR latch; this bit is write onPC4(PWRIN). If bit 4 (PWREDGE) is low, then the ly. Undefined after Reset. latch will be triggered on the falling edge of the signal at PC4(PWRIN). The PWR latch can be reset IRINTEN. This bit enables the IRINTN signal (#0) by setting bit 6 (RESPWRLAT) of the latches reg.com latch to the ST638x core. Undefined after from the ister; the bit is set only and a high should be written reset. every time the PWR latch needs to be reset. If bit 5 IRPOSEDGE. The bit determines the edge which (PWRINTEN) of the latches register (E9h) is high, will cause the IR latch to be set. If this bit is high, then the output of the PWR latch, PWRINTN, may than the IR latch will be set on the rising edge of generate an interrupt (#4). PWRINTN is inverted the IR signal. Undefined after reset. with respect to the state of the PWR latch. If bit 5 Bit 0. This bit is not used (PWRINTEN) is low, then the output of the PWR latch, PWRINTN, is forced high.
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4.8 ON-SCREEN DISPLAY (OSD) The OSD macrocell is a CMOS LSI character gen4.8.1 Format Specification erator which enables display of characters and The entire display can be turned on or off through symbols on the TV screen. The character rounding the use of the global enable bit or the display may function enhances the readability of the characbe selectively turned on or off by word. To turn off ters. The OSD macrocell receives horizontal and the entire display, the global enable bit (GE) vertical synchronization signal and outputs screen should be zero. If the global enable bit and the information via R, G, B and blanking pins. OSD ram enable bit are one, the display is controlThe main characteristics of the macrocell are listled by the word enable bit (WE). The global enable ed below bit and the OSD ram enable bit are located in the global enable register and the word enable bit is - Number of display characters: 8 lines by 20 collocated in the space character preceding the word. umns. Each line must begin with a format character - Number of character types: 192 characters in which describes the format of that line and of the one bank. first word. This character is not displayed. - Character size: Four character heights (18H, A space character defines the format of the subse36H, 54H, 72H), programmable by line. quent word. A space character is denoted by a pair - Character format: 14x18 dots with character of one in bits 7 (MSB) and 6 of the character regisrounding function. ter in the display RAM. If bit 7 and 6 of a character register are different from "11", the 8 bits of the - Character colour: Eight colours available procharacter register are used as an index which segrammable by word. lects the desired character font from the 192 char- Display position: 63 horizontal positions proacters ROM. grammable by 2/fOSC and 63 vertical positions The character colour and background can be proprogrammable by 4H grammed by word. This information is encoded in - Word spacing: 64 positions programmable from the space character between words or in the for2/f OSC to 128/fOSC mat character at the beginning of each line. Four - Line spacing: 63 positions programmable .com from 4 bits define the colour and background of the folto 252 H with two line spacing values per screen. lowing word. - Background: No background, square backCharacters are defined in a 14 x 18 dots format. ground or fringe background. The presence of One dot is defined vertically as 1H (horizontal line) background is programmable by word, the mode per field (2H per frame) and horizontally as 1/fOSC (fringe or square) being the same for the entire if the smallest character size is enabled. The screen. rounding function is not available for the smallest character size. For the other sizes, the rounding - Background colour: Two types selected by word function could be disabled by the rounding disable from a palette of eight colours. The palette is probit (RDIS). There is no space between characters grammable by screen. or lines if the vertical space enable (VSE) and hor- Display output: Three video signal output termiizontal space enable (HSE) bits are both zero. nals (R,G,B) and a blank output terminal. This allows the use of special graphic characters - Display on/off: Display data may be programmed (combination of two or more characters). on or off by word or entire screen. The entire The normal alphanumeric character set is formatscreen may be blanked. ted to be 13 x 16 with one empty row at the top and - Full screen background: Background on the enone at the bottom and one empty column at the tire TV screen, one of eight colours available, right. If VSE and HSE are both zero, then the with normal text display possible. spacing between alphanumeric characters is 1 dot and the spacing between lines of alphanumeric characters is 4H per frame.
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ON-SCREEN DISPLAY (Cont'd) The character size is programmed by line through the use of the size bits (S1 and S2) in the format character. The vertical spacing enable bit (VSE) located in the format character controls the spacing between lines. If this bit is set to one, the spacing between lines is defined by one of the vertical spacing register, otherwise the spacing between lines is 0. As there are two vertical space registers available, the actual spacing between two successive lines will be selected by the vertical space select bit (VSS) in the format character. The spacing between words is controlled by the horizontal space enable bit (HSE) located in the space character. If this bit is set to one, the spacing between words is defined by the horizontal spacing register, otherwise the space character width of 14 dots is the spacing between words. The formats for the format character, display character and space character are described hereafter. 4.8.2 Format Character Register (FT) See Data RAM Table Description for Specific Address -- Read/Write Table 16. Format Character Register Colour Setting.
R 0 0 0 0 1 1 1 1 G 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 Colour Black Blue Green Cyan Red Magenta Yellow White
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BGS. Background Select. The background select bit selects the desired background for the following word. There are two possible backgrounds defined by the bits in the Background Control Register. "0" The background on the following word is enabled by BG0 and the colour is set by R0, G0, and B0. "1" The background on the following word is enabled by BG1 and the colour is set by R1, G1, and B1. 7 0 VSE. Vertical Space Enable. The vertical space S2 S1 R G B BGS VSS VSE enable .com bit determines the spacing between lines. "0" The space between lines is equal to 0H. The alphanumeric character set is implemented in S1-S2. Character Size. The character size bits a 13 x 16 format with one empty column to the specify the character size for each line as defined left and one empty row above and one below in Table 15. and stored in a 14 x 18 format. Table 15. Format Character Register Size "1" The space between lines is defined by the valSetting ues in the vertical space register and the value of the VSS bit. Vertical Horizontal S2 S1 Height length VSS. Vertical Space Select. If the VSE bit is set, the value of this bit selects one of the two ver1 1 18H 14 TDOT tical spaces contained in the vertical space 1 0 36H 28 TDOT registers (VSR0 and VSR1). A "0" in this bit 0 1 54H 42 TDOT selects the VSR0 value, a "1" selects the VSR1 value, respectively. 0 0 72H 56 TDOT Note. The first word of each line is always enaTDOT= 1/fosc bled. If we desire the line to begin further to the right we have two solutions: to increase the R, G, B. Colour. The 3 colour control bits define HSAR register or to introduce a Space Charthe foreground colour of the following word as acter just after the Format Character. A Space shown in Table 16. Character should also be used if we don't want the current line to be displayed.
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ON-SCREEN DISPLAY (Cont'd) Display Character Register (Ch) See Data RAM Table Description for Specific Address -- Read/Write "1" The background on the following word is enabled by BG1 and the colour is set by R1, G1, and B1. WE. Word Enable. The word enable bit defines 7 0 whether or not the following word is displayed. "0" The word is not displayed. C7 C6 C5 C4 C3 C2 C1 C0 "1" If the global enable bit and the OSD ram enable bit are set, then the word is displayed. C7-C6. This bits must be different from "11". HSE. Horizontal Space Enable. The horizontal C7-C0. Character code. The 8 bits character code space enable bit determines the spacing between (range: 00h to 0BFh) selects the character from a words. set of 192 characters available. "0" The space between words is equal to the width of the space character, which is 14 dots. Space Character Format Register (Ch) "1" The space between words is defined by the value in the horizontal space register plus the See Data RAM Table Description for Specific Adwidth of the space character. dress -- Read/Write Character Set 7 0 The character set is user defined as ROM mask D7 D6 R G B BGS WE HSE option. Register and RAM Addressing The OSD contains eight registers and 168 RAM loD7-D6. This bits must be "11". cations. The eight registers are the Vertical Start R, G, B. Colour. The 3 colour control bits define Address register, Horizontal Start Address registhe foreground colour of the following word as ter, Vertical Space registers (VSR0 and VSR1), shown in table below. Horizontal Space register, Background Control .com Global Enable register and Polarity Select register, Table 17. Space Character Register Colour register (PSR). The Global Enable register and Setting. Polarity Select register can be written at any time by the ST6 Core. The access to the next five regR G B Colour isters and the RAM is controlled through the state 0 0 0 Black of the Global Enable register. 0 0 1 Blue The first six registers and the RAM are located in page 5 of the paged memory of the ST6388 MCU. 0 1 0 Green This page contains 64 memory locations. This 0 1 1 Cyan paged memory is mapped into the memory loca1 0 0 Red tions 00h to 3Fh of the ST6388 memory map. A page of memory is enabled by setting the desired 1 0 1 Magenta page bit, located in the Data Ram Bank Register, 1 1 0 Yellow to a one. The page register is at location E8h. The 1 1 1 White hexadecimal value 20h selects page 5 - the OSD RAM and registers (except PSR). As the OSD RAM consists of 168 words, this RAM is further BGS. Background Select. The background select paged using two bits (LS1/LS0) in the Global Enabit selects the desired background for the following ble register, in order to fit onto the 64 locations of word. There are two possible backgrounds defined the page 5 of the MCU RAM space. Table 18 by the bits in the Background Control Register. shows the addresses of the OSD registers and "0" The background on the following word is enaRAM. bled by BG0 and the colour is set by R0, G0, and B0.
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ON-SCREEN DISPLAY (Cont'd) Table 18. OSD Control Registers and Data RAM Addressing
Page Page 5 Page 5 Page 5 Page 5 Page 5 Page 5 Page 5 Page 5 Page 5 Static page Address 00h - 14h 20h - 34h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Fh EDh Register or RAM RAM Locations 00h - 14h RAM Locations 20h - 34h Vertical Start Register Horizontal Start Register Vertical Space Register 0 Horizontal Space Register Background Control Register Vertical Space Register 1 Global Enable Register OSD Polarity Select Register
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OSD Global Enable Register This register contains the global enable bit (GE), OSD Ram Enable bit (ORE) and the line select bits 7 0 (LS1/LS0). This register can be written at any time. It is a write only register. D7 D6 D5 D4 VSP HSP BLKP RGBP OSD Global Enable Bit Register (OGER) Address: 3Fh - Page 5 -- Write Only D7-D4. These bits are reserved and must always .com with 0. be written
7 0 D7 D6 D5 D4 LS1 LS0 ORE GE
"0" The OSD RAM can be accessed by the Core. "1" The OSD RAM content is displayed on screen and cannot be accessed by Core. Note: The display of characters on screen is only possible after the setting of these two bits LS1-LS0. This bits selects one pair of OSD RAM lines that is to be mapped into the 0h-35h address area. There are four possible values of this pair of bits: "00" - selects line 0 and line 1; "01" - selects line 2 and line 3; "10" - selects line 4 and line 5; "11" - selects line 6 and line 7. Note: The global registers in page 5 are accessible at RAM locations 38h-3Fh, page 5 selected, regardless of the value of the LS0/LS1 bits. OSD Polarity Select Register (OPSR) Address: EDh - Static Page -- Write Only
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D7-D4. These bits are not used GE. Global Enable. This bit allows the entire display to be turned off. "0" The entire display is disabled. The other registers of the OSD can be accessed by the Core. "1" Display of words is controlled by the word enable bits (WE) located in the format or space character. The other registers cannot be accessed by the Core. ORE. OSD Ram Enable. This bit controls the access to the OSD RAM.
VSP. Vertical sync polarity input select bit. This bit selects the polarity of the VSync input signal ("0" for positive, "1" for negative polarity, respectively). HSP. Horizontal sync input polarity select bit. This bit selects the polarity of the HSync input signal ("0" for positive, "1" for negative polarity, respectively). BLKP. Blanking output polarity select bit. This bit selects the polarity of the BLK output ("0" for positive, "1" for negative polarity, respectively). RGBP. RGB output polarity select bit. This bit selects the polarity of the RGB outputs ("0" for positive, "1" for negative polarity, respectively). Note: Reset value is 00h, all polarities being positive.
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ON-SCREEN DISPLAY (Cont'd) Vertical Start Address Register (VSAR) Address: 38h - Page 5 -- Read/Write
7 D7 FR VSA5 VSA4 VSA3 VSA2 VSA1 0 VSA0
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D7. This bit is not used FR. FRinge background.This bit changes the background from a box background to a fringe background. The background is enabled by word as defined by either BG0 or BG1. "0" The background is defined to be a box which is 15 x 18 dots (the 14x18 dots frame of the character + one dot column placed left of the character frame). "1" The background is defined to be a fringe. The fringe background is complete around the displayed character provided that it is inside the 15x18 dots frame. Note: For the smallest character size (14TDOT, 18H) the fringe function may be either a full fringe or a shadow background (see also FF_SH bit of the VSR1 register). 7 0 VSA5-VSA0. Vertical Start Address. These bits D7 determine the start position of the first.com SCB VS5 VS4 VS3 VS2 VS1 VS0 line in the vertical direction. The 6 bits can specify 63 display start positions of interval 4H. The first D7. This bit is not used start position will be the fourth line of the display. The vertical start address is defined SCB. Screen Blanking. This bit allows the entire screen to be blanked. VSA0 by the following formula. 5 (VSA5) + 24 "0" The blanking output signal BLANK is active Vertical Start Address = 4H(2 only when displaying characters. (VSA4) +23 (VSA3) + 22 (VSA2) + 21 (VSA1) + 20 (VSA0)) "1" The blanking output signal BLANK is always Note: The case of all Vertical Start Address bits active. Characters in the display RAM are still being zero is illegal. displayed. Horizontal Start Address Register (HSAR) When this bit is set to one, the screen is blanked also without setting the Global Enable bit to one Address: 39h - Page 5 -- Read/Write (OSD disabled). 7 0 VS5, VS0. Vertical Space. These bits determine the spacing between lines if the Vertical Space EnD7 SBD HSA5 HSA4 HSA3 HSA2 HSA1 HSA0 able bit (VSE) in the format character is set and the Vertical Space Select bit (VSS) is reset. If VSE is zero there will be no spaces between lines. The D7. This bit is not used. Vertical Space bits can specify one of 63 spacing values from 4H to 252H. The space between lines SBD. Space Background Disable. This bit controls is defined by the following formula. whether or not the background is displayed on space characters. If two background colours are Space between lines = 4H(25 (VS5) + 24 (VS4) + used on adjacent words, then the background 23 (VS3) + 2 2 (VS2) + 2 1 (VS1) + 20 (VS0)) should not be displayed on spaces in order to Note: The case of all Vertical Space bits being make a nice break between colours. If an even zero is not legal. background around an area of text is desired, as in
a menu, then the background should be displayed when on space characters. "0" The background during spaces is controlled by the background enable bits (BG0 and BG1) located in the Background Control register. "1" The background is not displayed when spaces are displayed. HSA5, HSA0 - Horizontal Start Address bits. These bits determine the start position of the first character in the horizontal direction. The 6 bits can specify 64 display start positions of interval 2/fOSC or 400ns. The first start position will be at 7.2s because of the time needed to access RAM and ROM before the first character can be displayed. The horizontal start address is defined by the following formula. Horizontal Start Address = 2/fOSC(18 + 25 (HSA5) +24 (HSA4) + 23 (HSA3) + 22 (HSA2) + 21 (HSA1) + 20 (HSA0)) Note: The case of all Horizontal Start Address bits being zero is illegal. Vertical Space Register 0 (VSR0) Address: 3Ah - Page 5 -- Read/Write
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ON-SCREEN DISPLAY (Cont'd) Horizontal Space Register (HSR) Address: 3Bh - Page 5 -- Read/Write
7 RDIS FSB HS5 HS4 HS3 HS2 HS1 0 HS0
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RDIS. Rounding DISable. This bit disable the rounding function for the following screen. It allows the display of some special characters which could be modified by the rounding function. "0"Rounding function enable 7 0 "1"Rounding function disable FSB. Full Screen Background. This bit allows the R1 R0 G1 G0 B1 B0 BK1 BK0 entire screen to be filled with a one colour background. The background is controlled by the background select bit (BGS). During this mode the disR1,R0,G1,G0,B1,B0. Background Colour. play of characters is possible. These bits define the colour of the specified back"0"No Full Screen Background ground, either background 1 or background 0 as defined in table below. "1"Full Screen Background is active Note: The full screen background bit has priority Table 19. Background Register Colour Setting. over the background enable bits (BK0 and BK1) and on the screen blanking bit. This means that if RX GX BX Colour the two backgrounds are disabled and the screen 0 0 0 Black blanking is active, the full screen background will still be displayed. 0 0 1 Blue .com HS5, HS0. Horizontal Space. These bits deter0 1 0 Green mine the spacing between words if the Horizontal 0 1 1 Cyan Space Enable bit (HSE) located in the space char1 0 0 Red acter is a one. The space between words is then equal to the width of the space character plus the 1 0 1 Magenta number of dots specified by the Horizontal Space 1 1 0 Yellow bits. The 6 bits can specify one of 64 spacing val1 1 1 White ues ranging from 1/fosc to 64/fosc. The formula is shown below for the smallest size character(18H). If larger size characters are being displayed the BK1,BK0. Background Enable.These bits deterspacing between words will increase proportionmine if the specified background is enabled or not. ately. Multiply the value below by 2, 3 or 4 for char"0" The word having this background specified acter sizes of 36H, 54H and 72H respectively. has not a background. 5 4 Space between words =2/fOSC(1+2 (HS5)+2 3 (HS3) +22 (HS2)+ 21 (HS1)+20 (HS0)) "1" The word having this background specified (HS4)+2 has a background of the colour selected by the corresponding RGB bits.
Note: This size does not include the width of the space character. The case of all Vertical Start Address bits being zero is illegal. Background Control Register (BCR) This register sets up two possible backgrounds. The background select bit (BGS) in the format or space character will determine which background is selected for the current word. Background Control Register Address: 3Ch - Page 5 -- Read/Write
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ON-SCREEN DISPLAY (Cont'd) Vertical Space Register 1 (VSR1) Address: 3Dh - Page 5 -- Read/Write
7 D7 FF_SH VS5 VS4 VS3 VS2 VS1 0 VS0
D7. This bit is not used FF_SH. Full fringe / shadow background select. This bit selects between the fringe and shadow backgrounds for the smallest size (18H) characters, provided that the FR bit is also set. "1" The 18H characters are surrounded by a fringe background. (Provided that FR bit is set and the selected background is active). This consists of a one dot wide contour in the background colour
"0" The 18H characters have a shadow background. (provided also that FR bit is set and the selected background is active). This consists of a one dot wide line on the right and lower sides of the character. VS5, VS0. Vertical Space. These bits determine the spacing between lines if the Vertical Space Enable bit (VSE) in the format character is set and the Vertical Space Select bit (VSS) is set. If VSE is zero there will be no spaces between lines. The Vertical Space bits can specify one of 63 spacing values from 4H to 252H. The space between lines is defined by the following formula. Space between lines = 4H(25 (VS5) + 24 (VS4) + 23 (VS3) + 2 2 (VS2) + 2 1 (VS1) + 20 (VS0)) Note: The case of all Vertical Space bits being zero is not legal.
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ON-SCREEN DISPLAY (Cont'd) OSD Data RAM The contents of the data RAM can be accessed by the ST6388 MCU only when the Global Enable bit (GE) in the Global Enable register is a zero. The first character in every line is the format character. This character is not displayed. It defines the size of the characters in the line and contains the vertical space enable bit. This character also defines the colour, background and display enable for the first word in the line. Subsequent characTable 20. OSD RAM Map
Column A0 A1 A2 A3 A4 LS1 0 0 0 0 LS0 0 0 1 1 0 0 1 1 A5 0 1 0 1 0 1 0 1 LINE 1 2 3 4 5 6 7 8 FT FT FT FT FT FT FT FT Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch ... ... ... ... ... ... ... Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch 0 0 0 0 0 0 1 1 0 0 0 0 2 0 1 0 0 0 3 1 1 0 0 0 4 0 0 1 0 0 ... ... ... ... ... ... 14 0 1 1 1 0 15 1 1 1 1 0 16 0 0 0 0 1 17 1 0 0 0 1 18 0 1 0 0 1 19 1 1 0 0 1 20 0 0 1 0 1
ters are either spaces or one of the 192 available character types. The space character defines the colour, background, display enable and horizontal space enable for the following word. Since there are 8 display lines of 20 characters each, the display RAM must contain 8 lines x (20 characters + 1 format character) or 168 locations. The RAM size is 168 locations x 8bits. The data RAM map is shown in Table 20.
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1 1 1 1
Ch .com ... Ch Ch Ch
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AVAILABLE SCREEN SPACE Notes: FT. The format character required for each line. Characters in columns1 through 20 are displayed. Ch. (Byte) Character (Index into OSD character generator) or space character
Emulator Remarks There are few differences between emulator and silicon. For noise reasons, the OSD oscillator pins
are not available: the internal oscillator can not be disabled and replaced by an external coil.
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ON-SCREEN DISPLAY (Cont'd) 4 - The timing of the on/off switching of the OSD 4.8.3 Application Notes oscillator is the following: 1- The OSD character generator is composed of a dual port video ram and some circuitry. It needs a. GE bit is set. The OSD oscillator will start on two input signals VSYNC and HSYNC to synchrothe next VSYNC signal. nize its dedicated oscillator to the TV picture. It b. GE bit is reset. The OSD oscillator will be imgenerates 4 output signals, that can be used from mediately switched off. the TV set to generate the characters on the screen. For instance, they can be used to feed the To avoid a bad visual impression, it is important SCART plug, providing an adequate buffer to drive that the GE bit is set before the end of the flyback the low impedance (75 ohm) of the SCART inputs. time when changing characters. This can be done inside the VSYNC interrupt routine. The following 2 - The Core sees the OSD as a number of RAM diagram can explain better: OSD Oscillator ON/ locations (168) plus a certain number of control OFF Timing registers (8). 175 of these locations are mapped in one page of the dynamic data ram address range Figure 32. OSD Oscillator ON/OFF Timing (0h...3Fh). VSYNC The page 5 (20h value loaded into the register 0E8h) is further subdivided in 4 pages (using bits LS1 and LS0) in order to allow access to all 168 BC E bytes of the OSD RAM within the allowed address VV V range. According to the value of these two bits we shall a first line (selected among lines 0, 2, 4 or 6) mapped onto the 0h-14h address range, and a second line (selected among lines 1, 3, 5 or 7) mapped onto the 20h-34h address range. time The global registers in page 5 are accessible at A D RAM locations 38h-3Fh, page 5 selected via DRBR, regardless of the value of the LS0/LS1 bits. VA00344 3 - The video RAM is a dual port ram. That .com means Notes:A - Picture time: 20 mS in PAL/SECAM. that it can be addressed either from the Core or from the OSD circuitry itself. To reduce the comB - VSYNC interrupt, if enabled. plexity of the circuitry, and thus its cost, some reC - Starting of OSD oscillator, if GE = 1. strictions have been introduced in the use of the D - Flyback time. OSD. When modifying the picture display (i.e.: a bar graph for an analog control), it is important that the a. The Core can access 6 of the global registers switching on of the GE bit is done before the end (addresses 38h - 3Dh in page 5) only when the of the flyback time (D in Figure 32). If the GE bit is OSD oscillator is OFF (GE bit not set). Only set after the end of the flyback time then the OSD the last location (control register 3Fh in page will not start until the beginning of the next frame. 5) can be addressed at any time. This is the This results in one frame being lost and will result Global Enable Register, which contains the in a flicker on the screen. One method to be sure GE and ORE bits. If the GE bit is set, the OSD to avoid the flicker is to wait for the VSYNC interis on, if it is reset the OSD is off. rupt at the start of the flyback; once the VSYNC inc. The Core can write to the 168 locations of terrupt is detected, then the GE and ORE bits can be set to zero, the global control registers OSD RAM only when the ORE bit is not set. changed, if necessary, and the GE set to one. All This bit must be set before the first active line this should occur before the end of the flyback time of OSD display (which displays characters). in order not to lose a frame. The correct edge of This line follows the VSYNC active period and the interrupt must be chosen. The characters in is delayed by a time equal to the Vertical Start RAM can be changed until the last line before the register value multiplied by the duration of one active screen area and then the ORE bit must be display line (64 s for the usual TV standard). set.
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ON-SCREEN DISPLAY (Cont'd) The VSYNC pin may alternatively be sampled by software in order to know the status; this can be done by reading bit 4 of register E4h; this bit is inverted with respect to the VSYNC pin. 6- The OSD oscillator external network should consist of a capacitor on each of the OSD oscillator pins to ground together with an inductance between pins. The user should select the two capacitors to be the same value (15pF to 25pF each is recommended). The inductance is chosen to give the desired OSD oscillator frequency for the application (typically 56H). 4.9 MIRROR REGISTER This an 8-bits Register at address DEh. It is undefined on Reset. After writing, the read value is the reversed byte: Bit0->Bit7, Bit1->Bit6, Bit2->Bit5, Bit3->Bit4, Bit4->Bit3, Bit5->Bit2, Bit6->Bit1, Bit7->Bit0 Note: Writing the XOR register affects the value of this register. 4.10 XOR REGISTER This an 8-bits Register at address DFh. It is undefined on Reset. To compute the XOR of two 8-bits values, the user has to write the first value in the MIRROR register (DEh) and then the second value in the XOR register (DFh). After that the XOR result can be read from the XOR register. To compute a new XOR with the result of the previous operation, the user can directly write the second value in the XOR register and read the XOR result in this same register. Note: writing the XOR register affects the value of the MIRROR register also.
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5 SOFTWARE
5.1 ST6 ARCHITECTURE The ST6 software has been designed to fully use the hardware in the most efficient way possible while keeping byte usage to a minimum; in short, to provide byte efficient programming capability. The ST6 core has the ability to set or clear any register or RAM location bit of the Data space with a single instruction. Furthermore, the program may branch to a selected address depending on the status of any bit of the Data space. The carry bit is stored with the value of the bit when the SET or RES instruction is processed. 5.2 ADDRESSING MODES bits of the opcode with the byte following the opcode. The instructions (JP, CALL) which use the extended addressing mode are able to branch to any address of the 4K bytes Program space. An extended addressing mode instruction is twobyte long. Program Counter Relative. The relative addressing mode is only used in conditional branch instructions. The instruction is used to perform a test and, if the condition is true, a branch with a span of -15 to +16 locations around the address of the relative instruction. If the condition is not true, the instruction which follows the relative instruction is executed. The relative addressing mode instruction is one-byte long. The opcode is obtained in adding the three most significant bits which characterize the kind of the test, one bit which determines whether the branch is a forward (when it is 0) or backward (when it is 1) branch and the four less significant bits which give the span of the branch (0h to Fh) which must be added or subtracted to the address of the relative instruction to obtain the address of the branch.
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The ST6 core offers nine addressing modes, which are described in the following paragraphs. Three different address spaces are available: Program space, Data space, and Stack space. Program space contains the instructions which are to be executed, plus the data for immediate mode instructions. Data space contains the Accumulator, the X,Y,V and W registers, peripheral and Input/ Output registers, the RAM locations and Data ROM locations (for storage of tables and constants). Stack space contains six 12-bit RAM cells Bit Direct. In the bit direct addressing mode, the used to stack the return addresses for subroutines .com set or cleared is part of the opcode, and bit to be and interrupts. the byte following the opcode points to the address of the byte in which the specified bit must be Immediate. In the immediate addressing mode, set or cleared. Thus, any bit in the 256 locations of the operand of the instruction follows the opcode Data space memory can be set or cleared. location. As the operand is a ROM byte, the immediate addressing mode is used to access conBit Test & Branch. The bit test and branch adstants which do not change during program execudressing mode is a combination of direct addresstion (e.g., a constant used to initialize a loop couning and relative addressing. The bit test and ter). branch instruction is three-byte long. The bit identification and the tested condition are included in Direct. In the direct addressing mode, the address the opcode byte. The address of the byte to be of the byte which is processed by the instruction is tested follows immediately the opcode in the Prostored in the location which follows the opcode. Digram space. The third byte is the jump displacerect addressing allows the user to directly address ment, which is in the range of -127 to +128. This the 256 bytes in Data Space memory with a single displacement can be determined using a label, two-byte instruction. which is converted by the assembler. Short Direct. The core can address the four RAM Indirect. In the indirect addressing mode, the byte registers X,Y,V,W (locations 80h, 81h, 82h, 83h) in processed by the register-indirect instruction is at the short-direct addressing mode. In this case, the the address pointed by the content of one of the ininstruction is only one byte and the selection of the direct registers, X or Y (80h,81h). The indirect reglocation to be processed is contained in the opister is selected by the bit 4 of the opcode. A regiscode. Short direct addressing is a subset of the diter indirect instruction is one byte long. rect addressing mode. (Note that 80h and 81h are also indirect registers). Inherent. In the inherent addressing mode, all the information necessary to execute the instruction is Extended. In the extended addressing mode, the contained in the opcode. These instructions are 12-bit address needed to define the instruction is one byte long. obtained by concatenating the four less significant
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5.3 INSTRUCTION SET The ST6 core offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. They can be divided into six different types: load/store, arithmetic/logic, conditional branch, control instructions, jump/call, and bit manipulation. The following paragraphs describe the different types. All the instructions belonging to a given type are presented in individual tables. Table 21. Load & Store Instructions
Instruction LD A, X LD A, Y LD A, V LD A, W LD X, A LD Y, A LD V, A LD W, A LD A, rr LD rr, A LD A, (X) LD A, (Y) LD (X), A LD (Y), A LDI A, #N LDI rr, #N Addressing Mode Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Direct Direct Indirect Indirect Indirect Indirect Immediate Immediate Bytes Cycles 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Flags Z * C * * * * * * * * * * * * * * * *
Load & Store. These instructions use one, two or three bytes in relation with the addressing mode. One operand is the Accumulator for LOAD and the other operand is obtained from data memory using one of the addressing modes. For Load Immediate one operand can be any of the 256 data space bytes while the other is always immediate data.
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Notes: X,Y. Indirect Register Pointers, V & W Short Direct Registers # . Immediate data (stored in ROM memory) rr. Data space register . Affected * . Not Affected
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INSTRUCTION SET (Cont'd) Arithmetic and Logic. These instructions are used to perform the arithmetic calculations and logic operations. In AND, ADD, CP, SUB instructions one operand is always the accumulator while the other can be either a data space memory conTable 22. Arithmetic & Logic Instructions
Instruction ADD A, (X) ADD A, (Y) ADD A, rr ADDI A, #N AND A, (X) AND A, (Y) AND A, rr ANDI A, #N CLR A CLR r COM A CP A, (X) CP A, (Y) CP A, rr CPI A, #N DEC X DEC Y DEC V DEC W DEC A DEC rr DEC (X) DEC (Y) INC X INC Y INC V INC W INC A INC rr INC (X) INC (Y) RLC A SLA A SUB A, (X) SUB A, (Y) SUB A, rr SUBI A, #N Addressing Mode Indirect Indirect Direct Immediate Indirect Indirect Direct Immediate Short Direct Direct Inherent Indirect Indirect Direct Immediate Short Direct Short Direct Short Direct Short Direct Direct Direct Indirect Indirect Short Direct Short Direct Short Direct Short Direct Direct Direct Indirect Indirect Inherent Inherent Indirect Indirect Direct Immediate Bytes 1 1 2 2 1 1 2 2 2 3 1 1 1 2 2 1 .com 1 1 1 2 2 1 1 1 1 1 1 2 2 1 1 1 2 1 1 2 2 Cycles 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Flags Z * C * * * * * * * * * * * * * * * * *
tent or an immediate value in relation with the addressing mode. In CLR, DEC, INC instructions the operand can be any of the 256 data space addresses. In COM, RLC, SLA the operand is always the accumulator.
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Notes: X,Y.Indirect Register Pointers, V & W Short Direct RegistersD. Affected # . Immediate data (stored in ROM memory)* . Not Affected rr. Data space register
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INSTRUCTION SET (Cont'd) Conditional Branch. The branch instructions achieve a branch in the program when the selected condition is met. Bit Manipulation Instructions. These instructions can handle any bit in data space memory. One group either sets or clears. The other group (see Conditional Branch) performs the bit test branch operations. Table 23. Conditional Branch Instructions
Instruction JRC e JRNC e JRZ e JRNZ e JRR b, rr, ee JRS b, rr, ee Branch If C=1 C=0 Z=1 Z=0 Bit = 0 Bit = 1 Bytes 1 1 1 1 3 3 Cycles 2 2 2 2 5 5 Flags Z * * * * * * C * * * *
Control Instructions. The control instructions control the MCU operations during program execution. Jump and Call. These two instructions are used to perform long (12-bit) jumps or subroutines call inside the whole program space.
Notes: b. 3-bit address e. 5 bit signed displacement in the range -15 to +16 ee. 8 bit signed displacement in the range -126 to +129
rr. Data space register . Affected. The tested bit is shifted into carry. * . Not Affected
Table 24. Bit Manipulation Instructions
Instruction Addressing Mode Bit Direct Bit Direct Bytes Cycles Flags Z * * C * *
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Notes: b. 3-bit address; rr. Data space register;
2 .com 4 2 4
* . Not Affected
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Table 25. Control Instructions
Instruction NOP RET RETI STOP (1) WAIT Addressing Mode Inherent Inherent Inherent Inherent Inherent Bytes 1 1 1 1 1 Cycles 2 2 2 2 2 Flags Z * * * * C * * * *
Notes: 1. This instruction is deactivatedand a WAIT is automatically executed instead of a STOP if the watchdog function is selected. . Affected *. Not Affected
Table 26. Jump & Call Instructions
Instruction CALL abc JP abc
Notes: abc. 12-bit address; * . Not Affected
Addressing Mode Extended Extended
Bytes 2 2
Cycles 4 4
Flags Z * * C * *
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Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6
LOW HI 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 0 0000 JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr RNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 1 0001 CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 0010 JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr 5 3 0011 4 0100 5 0101 2 # 4 x 1 # 4 a,x 1 # 4 y 1 # 4 a,y 1 # 4 v 1 # 4 a,v 1 # 4 w 1 # 4 a,w 1 sd 1 1 LD 2 e prc sd 1 2 e prc 1 JRC 1 INC 2 e prc 2 JRC 4 sd 1 2 e prc 1 JRC 4 1 LD 2 e prc 2 JRC 4 sd 1 2 e prc 1 JRC 4 1 INC 2 e prc JRC 4 sd 1 2 e prc 1 JRC # AND a,(x) ind ANDI a,nn imm SUB a,(x) ind SUBI a,nn imm DEC (x) ind # 1 LD 2 e prc JRC 4 (x),a ind sd 1 2 e prc 1 JRC 1 INC 2 e prc 2 JRC 4 sd 1 2 e prc 1 JRC 4 1 LD 2 e prc 2 JRC 4 sd 1 2 e prc 1 JRC 4 1 INC 2 e prc 2 JRC 4 e prc 1 JRC 4 6 0110 JRC 4 a,(x) ind LDI a,nn imm CP a,(x) ind CPI a,nn imm ADD a,(x) ind ADDI a,nn imm INC (x) ind # LD 7 0111 LD LOW HI 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111
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9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111
JRR 2 JRZ b0,rr,ee e 3 bt 1 pcr 5 JRS 2 JRZ b0,rr,ee e 3 bt 1 pcr 5 JRR 2 JRZ b4,rr,ee e 3 bt 1 pcr 5 JRS 2 JRZ b4,rr,ee e 3 bt 1 pcr 5 JRR 2 JRZ b2,rr,ee e 3 bt 1 pcr 5 JRS 2 JRZ b2,rr,ee e 3 bt 1 pcr 5 JRR 2 JRZ b6,rr,ee e 3 bt 1 pcr 5 JRS 2 JRZ b6,rr,ee e 3 bt 1 pcr 5 JRR 2 JRZ b1,rr,ee e 3 bt 1 pcr .com 5 JRS 2 JRZ b1,rr,ee e 3 bt 1 pcr 5 JRR 2 JRZ b5,rr,ee e 3 bt 1 pcr 5 JRS 2 JRZ b5,rr,ee e 3 bt 1 pcr 5 JRR 2 JRZ b3,rr,ee e 3 bt 1 pcr 5 JRS 2 JRZ b3,rr,ee e 3 bt 1 pcr 5 JRR 2 JRZ b7,rr,ee e 3 bt 1 pcr 5 JRS 2 JRZ b7,rr,ee e 3 bt 1 pcr
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Abbreviations for Addressing Modes: dir Direct sd Short Direct imm Immediate inh Inherent ext Extended b.d Bit Direct bt Bit Test pcr Program Counter Relative ind Indirect
Legend: # Indicates Illegal Instructions e 5 Bit Displacement b 3 Bit Address rr 1byte dataspace address nn 1 byte immediate data abc 12 bit address ee 8 bit Displacement
Cycle Operand Bytes Addressing Mode
2 e 1
JRC prc
Mnemonic
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Opcode Map Summary (Continued)
LOW HI 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 8 1000 JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr RNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 ext 1 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 9 1001 JP 2 A 1010 JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr 4 B 1011 C 1100 4 3 4 1 4 D 1101 LDI 2 rr,nn imm DEC x sd COM a e 1 2 e 1 2 e prc 1 JRC 4 e prc 2 JRC 4 e 1 4 y 1 2 1 4 y,a 1 # 4 v 1 4 a 1 4 v,a 1 2 1 4 w 1 2 1 4 w,a 1 sd 1 sd 1 WAIT 2 e inh 1 LD 2 e prc 2 prc 1 JRC 4 sd 1 RET 2 e inh 1 DEC 2 e prc 2 JRC 4 prc 1 JRC 4 inh 1 LD 2 e prc 2 JRC 4 sd 1 RCL 2 e prc 1 JRC 4 1 DEC 2 e prc 2 JRC 4 sd 1 2 e prc 1 JRC 4 sd 1 STOP 2 e inh 1 LD 2 e prc 2 JRC 4 prc 1 JRC 4 inh 1 DEC 2 e prc 2 JRC 4 prc 1 JRC 4 a,rr dir ADD a,(y) ind ADD a,rr dir INC (y) ind INC rr dir LD (y),a ind LD rr,a dir AND a,(y) ind AND a,rr dir SUB a,(y) ind SUB a,rr dir DEC (y) ind DEC rr dir prc 2 JRC 4 a,(y) ind CP prc 1 JRC 4 a,rr dir CP E 1110 JRC 4 a,(y) ind LD F 1111 LD LOW HI 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111
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9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111
RES 2 JRZ b0,rr e 2 b.d 1 pcr 4 SET 2 JRZ b0,rr e 2 b.d 1 pcr 4 RES 2 JRZ b4,rr e 2 b.d 1 pcr 4 SET 2 JRZ b4,rr e 2 b.d 1 pcr 4 RES 2 JRZ b2,rr e 2 b.d 1 pcr 4 SET 2 JRZ b2,rr e 2 b.d 1 pcr 4 RES 2 JRZ b6,rr e 2 b.d 1 pcr 4 SET 2 JRZ b6,rr e 2 b.d 1 pcr 4 RES 2 JRZ b1,rr e 2 b.d 1 pcr .com 4 SET 2 JRZ b1,rr e 2 b.d 1 pcr 4 RES 2 JRZ b5,rr e 2 b.d 1 pcr 4 SET 2 JRZ b5,rr e 2 b.d 1 pcr 4 RES 2 JRZ b3,rr e 2 b.d 1 pcr 4 SET 2 JRZ b3,rr e 2 b.d 1 pcr 4 RES 2 JRZ b7,rr e 2 b.d 1 pcr 4 SET 2 JRZ b7,rr e 2 b.d 1 pcr
4 x,a 1 2
1 LD 2 sd 1 RETI 2
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Abbreviations for Addressing Modes: dir Direct sd Short Direct imm Immediate inh Inherent ext Extended b.d Bit Direct bt Bit Test pcr Program Counter Relative ind Indirect
Legend: # Indicates Illegal Instructions e 5 Bit Displacement b 3 Bit Address rr 1byte dataspace address nn 1 byte immediate data abc 12 bit address ee 8 bit Displacement
Cycle Operand Bytes Addressing Mode
2 e 1
JRC prc
Mnemonic
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ST6380, ST6381, ST6382, ST6383, ST6388, ST6389
6 ELECTRICAL CHARACTERISTICS
6.1 ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs against damage due to high static voltages, however it is advised to take normal precaution to avoid application of any voltage higher than maximum rated voltages. For proper operation it is recommended that VI and VO must be higher than VSS and smaller than VDD. Reliability is enhanced if unused inputs are connected to an appropriated logic voltage level (VDD or VSS). Power Considerations.The average chip-junction temperature, Tj, in Celsius can be obtained from: Tj= TA + PD x RthJA Where: TA = Ambient Temperature. RthJA =Package thermal resistance (junction-to ambient). PD = Pint + Pport. Pint = IDD x VDD (chip internal power). Pport = Port power dissipation (determined by the user).
Value -0.3 to 7.0 VSS - 0.3 to +13 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to +13 VSS - 0.3 to VDD + 0.3 + 10 + 50 50 150 150 -60 to 150 Unit V V V V V mA mA mA mA C C
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Symbol VDD VI VI VO VO IO IO IVDD IVSS Tj TSTG
Parameter Supply Voltage Input Voltage (ADC IN) Input Voltage (Other inputs) Output Voltage (PA4-PA7, PC4-PC7, DA0-DA5) Output Voltage (Other outputs) Current Drain per Pin Excluding VDD, VSS , PA6, PA7 Current Drain per Pin (PA6-PA7) Total Current into VDD (source) .com Total Current out of VSS (sink) Junction Temperature Storage Temperature
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Note: Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
Symbol RthJA Parameter Thermal Resistance Test Conditions PSDIP42 Min. Value Typ. Max. 67 Unit C/W
6.2 RECOMMENDED OPERATING CONDITIONS
Symbol TA VDD fOSC fOSDOSC Parameter Operating Temperature Operating Supply Voltage Oscillator Frequency RUN & WAIT Modes On-screen Display Oscillator Frequency Test Conditions 1 Suffix Versions Min. 0 4.5 Value Typ. 5.0 8 Max. 70 6.0 8.1 8.0 Unit C V MHz MHz
EEPROM INFORMATION The ST63xx EEPROM single poly process has been specially developed to achieve 300.000 Write/Erase cycles and a 10 years data retention.
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ST6380, ST6381, ST6382, ST6383, ST6388, ST6389
6.3 DC ELECTRICAL CHARACTERISTICS (TA = 0 to +70C unless otherwise specified). Table 27: DC ELECTRICAL CHARACTERISTICS
Symbol VIL VIH VHYS Parameter Input Low Level Voltage Input High Level Voltage Hysteresis Voltage(1) Test Conditions All I/O Pins All I/O Pins All I/O Pins VDD = 5V DA0-DA5, PB0-PB6, OSD Outputs, PC0-PC7, O0, O1, PA0-PA5 VDD = 4.5V IOL = 1.6mA IOL = 5.0mA PA6-PA7 VDD = 4.5V IOL= 1.6mA IOL= 25mA OSDOSCout OSCout VDD = 4.5V IOL= 0.4mA VS Output VDD = 4.5V IOL= 0.5mA IOL= 1.6mA .com OSD PB0-PB6, PA0-PA3, Outputs VDD = 4.5V IOH = - 1.6mA OSDOSCout, OSCout, VDD = 4.5V IOH= - 0.4mA VS Output VDD = 4.5V IOH= - 0.5mA PB0-PB6, PA0-PA3, PC0-PC3, VIN= VSS OSCin VIN= VSS OSCin VIN= VSS VIN= VDD OSCin All I/O Input Mode no pull-up OSDOSCin VIN= VDD or VSS Min. 0.8xVDD 1.0 Value Typ. Max. 0.2xVDD Unit V V V
VOL
Low Level Output Voltage
0.4 1.0
V V
VOL
Low Level Output Voltage
0.4 1.0 0.4
V V V
VOL
Low Level Output Voltage
VOL
Low Level Output Voltage
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VOH High Level Output Voltage
0.4 1.0 4.1
V V V
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VOH
High Level Output Voltage
4.1
V
VOH
High Level Output Voltage Input Pull Up Current Input Mode with Pull-up Input Pull Up Current Input Leakage Current Input Pull-down current in RESET Input Leakage Current RAM Retention Voltage in RESET Mode Input Leakage Current
4.1
V
IPU IPU IIL IIH IIL IIL IIH VDDRAM IIL IIH
- 100 - 50 - 10 0.1 100
- 50 - 25 -1 1
- 25 - 10 - 0.1 10
A A A A A
-10
10
1.5 Reset Pin with Pull-up VIN= VSS - 50 - 30 - 10
V A
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ST6380, ST6381, ST6382, ST6383, ST6388, ST6389
Table 27: DC ELECTRICAL CHARACTERISTICS
Symbol IOH Parameter Output Leakage Current Output Leakage Current High Voltage Supply Current RUN Mode Supply Current WAIT Mode Supply Current at transition to RESET Reset Trigger Level ON Reset Trigger Level OFF Input Level Relatice Tolerance(1) Test Conditions DA0-DA5, PA4-PA5, PC0-PC7, O0, O1 VOH = VDD DA0-DA5, PA4-PA7, PC4-PC7, O0, O1 VOH = 12V fOSC = 8MHz, ILoad= 0mA VDD= 6.0V fOSC= 8MHz, ILoad= 0mA VDD= 6V fOSC= Not App, ILoad= 0mA VDD= 6V RESET Pin RESET Pin A/D AFC Pin Relative to other levels VDD= 5V 0.8xVDD 100 Min. Value Typ. Max. 10 Unit A A mA mA mA V V mV
IOH IDD IDD IDD VON VOFF VTR
40 6 3 0.1 16 10 1 0.3xVDD
Note 1. Not 100% Tested
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6.4 AC ELECTRICAL CHARACTERISTICS (TA = 0 to +70C, fOSC=8MHz, VDD=4.5 to 6.0V unless otherwise specified)
Symbol tWRES tOHL tOHL Parameter Minimum Pulse Width High to Low Transition Time High to Low Transition Time Test Conditions RESET Pin PA6, PA7 VDD = 5V, CL = 100pF (2) DA0-DA5, PB0-PB6, OSD Outputs, PC0-PC7 VDD = 5V, CL = 100pF PB0-PB6, PA0-PA3, OSD Outputs, PC0-PC3 VDD = 5V, CL = 100pF Min. 125 Value Typ. Max. Unit ns 100 20 ns ns
tOLH fDA
Low to High Transition Time
20 31.25 62.50 5 >1 million
ns kHz kHz ms cycles years pF pF pF 25 pF
D/A Converter Repetition Frequency (1) SIO Baudrate (1) fSIO EEPROM Write Time tWEE EEPROM WRITE/ERASE CyEndurance cles Retention EEPROM Data Retention (4) Input Capacitance (3) CIN COUT Output Capacitance (3) COSCin, Oscillator Pins Internal (3) COSCout Capacitance
TA = 25C One Byte QA LOT Acceptance Criteria TA = 25C All Inputs Pins All Outputs Pins
10
300,000 10
10 10 5
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COSDin, Oscillator Pins External (3) COSDout Capacitance
Recommended .com
15
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Notes: 1. A clock other than 8MHz will affect the frequency response of those peripherals (D/A, and SPIs) whose clock is derived from the system clock. 2. The rise and fall times of PORT A have been increased in order to avoid current spikes while maintaining a high drive capability 3. Not 100% Tested 4. Based on extrapolated data
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ST6380, ST6381, ST6382, ST6383, ST6388, ST6389
7 GENERAL INFORMATION
7.1 PACKAGE MECHANICAL DATA Figure 33. 42-Pin Plastic Shrink Dual-In-Line Package
Dim. A
E A2 A1 A L e b2 D b C E1 eA eB E .015 GAGE PLANE LEAD DETAIL eB
mm Min 0.51 3.05 0.46 0.56 1.02 1.14 0.23 15.24 1.78 15.24 18.54 1.52 0.000 2.54 Typ Max 5.08 0.020 Min
inches Typ Max 0.200
A1 A2 b b2 C D E E1 e eA
VR01725G eC
3.81 4.57 0.120 0.150 0.180 0.018 0.022 0.040 0.045
0.25 0.38 0.009 0.010 0.015 16.00 0.600 0.070 0.600 0.730 0.060 0.630
36.58 36.83 37.08 1.440 1.450 1.460 12.70 13.72 14.48 0.500 0.540 0.570
eB eC L N
3.30 3.56 0.100 0.130 0.140 Number of Pins 42
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7.2 ORDERING INFORMATION The following chapter deals with the procedure for transfer the Program/Data ROM codes to STMicroelectronics. Communication of the ROM Codes. To communicate the contents of Program/Data ROM memories to STMicroelectronics, the customer must send: - one file in INTEL INTELLEC 8/MDS FORMAT for the PROGRAM Memory; - one file in INTEL INTELLEC 8/MDS FORMAT for the EEPROM initial content (this file is optional). - two files in INTEL...FORMAT for the OSD font memory - the option list described below. The program ROM should respect the ROM Memory Map as in Table 4 on page 10. The ROM code must be generated with an ST6 assembler. Before programming the EPROM, the EPROM programmer buffer must be filled with FFh.
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ST6380, ST6381, ST6382, ST6383, ST6388, ST6389
GENERAL INFORMATION (Cont'd) 7.3 CUSTOMER EEPROM INITIAL CONTENTS: a. The content should be written into an INTEL INTELLEC format file. b In the case of 384 bytes of EEPROM, the starting address is 000h and the end address is 17Fh. The order of the pages (64 bytes each) is an in the specification (i.e. b7, b1 b0: 001, 010, 011, 101, 110. 111). c. Undefined or don't care bytes should have the content FFh. 7.4 OSD Test Character Figure 34. OSD Test Character
1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 2 3 4 5 6 7 8 9 10 11 12 13 14
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IN ORDER TO ALLOW THE TESTING OF THE ON-CHIP OSD MACROCELL THE FOLLOWING CHARACTER MUST BE PROVIDED AT THE FIXED BFh (191) POSITION. Listing Generation & Verification. When STMicroelectronics receives the files, a computer listing is generated from them. This listing refers extractly to the mask that will be used to produce the microcontroller. Then the listing is returned to the customer that must thoroughly check, complete, sign and return it to STMicroelectronics. The signed list constitutes a part of the contractual agreement for the creation of the customer mask. STMicroelec.com tronics sales organization will provide detailed information on contractual points. 7.5 ORDERING INFORMATION TABLE
Sales Type ST6380B1/ XXX ST6380B4/ XXX ST6381B1/ XXX ST6381B4/ XXX ST6382B1/ XXX ST6382B4/ XXX ST6383B1/ XXX ST6383B4/ XXX ST6388B1/ XXX ST6388B4/ XXX ST6389B1/ XXX ST6389B4/ XXX ROM/ EEPROM Size 8K/ 384 Bytes 8K/ 384 Bytes 8K/ 384 Bytes 8K/ 384 Bytes 14K/ 384 Bytes 14K/ 384 Bytes 14K/ 384 Bytes 14K/ 384 Bytes 20K/ 384 Bytes 20K/ 384 Bytes 20K/ 384 Bytes 20K/ 384 Bytes D/ A Converter 6 6 4 4 6 6 4 4 6 6 4 4 Temperature Range 0 to + 70 C -10 to + 70 C 0 to + 70 C -10 to + 70 C 0 to + 70 C -10 to + 70 C 0 to + 70 C -10 to + 70 C 0 to + 70 C -10 to + 70 C 0 to + 70 C -10 to + 70 C Package PSDIP42 PSDIP42 PSDIP42 PSDIP42 PSDIP42 PSDIP42 PSDIP42 PSDIP42 PSDIP42 PSDIP42 PSDIP42 PSDIP42
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Note: "XXX" Is the ROM code identifier that is allocated by STMicroelectronics after receipt of all required options and the related ROM file.
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ST6380, ST6381, ST6382, ST6383, ST6388, ST6389
ST63 ROM MICROCONTROLLER FAMILY OPTION LIST Customer ................................................................ Address ................................................................ Contact ................................................................ Phone No ................................................................ Reference ............................................................... ST638X SERIES Device (Put a cross on selected item) : ST6365 [ ] ST6381 [ ] ST6367 [ ] ST6368 [ ] ST6380 [ ] ST6375 [ ] ST6377 [ ] ST6383 [ ] ST6378 [ ] ST6382 [ ] ST6385 [ ] ST6389 [ ] ST6387 [ ] ST6388 [ ] Package [ ] (p) Temperature Range [ ] (t) Special Marking [ ] (y/n)
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.com Traceability marking (mandatory) (p) B = Dual in Line Plastic T = Thin Quad Flat (not available on all products) (t) 1 = 0 to +70 C 4 = -10 to +70 C (only for ST6368/78/80/81/82/83/88/89) (N) Letters, digits, '.', '-', '/' and spaces only
ST638X OPTION LIST OSD Polarity Options (Put a cross on selected item) : (No option list for ST6380/81/82/83/88/89) POSITIVE NEGATIVE VSYNC, HSYNC [] [] R,G,B [] [] BLANK [] []
Line 1 Line 2 Line 3
".............." (N) ".............." (N) ".............." (N)
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ST638X CHECK LIST YES NO ROM CODE [] [] OSD Code: ODD & EVEN [] [ ] For ST6365/67/75/77/85/87 OSD Code: [] [ ] For ST6368/78/80/81/82/83/88/89 EEPROM Code (If Desired) [] [ ] Only for ST6365/67/75/77/85/87 Notes .................................................................. .................................................................. Signature ................... Date ..........
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Notes:
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ST63E88,ST63T88, ST63E89,ST63T89
8-BIT MCUs WITH ON-SCREEN-DISPLAY FOR TV TUNING
s s s s s s s s s
s
s s
s
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s s s s
s s
s
s
4.5 to 6V supply operating range 8MHz Maximum Clock Frequency User Program EPROM: up to 20140 bytes Reserved Test EPROM: up to 340 bytes Data ROM: user selectable size Data RAM: 256 bytes Data EEPROM: 384 bytes 42-Pin Shrink Dual in Line Plastic Package Up to 22 software programmable general purpose Inputs/Outputs, including 2 direct LED driving Outputs Two Timers each including an 8-bit counter with a 7-bit programmable prescaler PSDIP42 Digital Watchdog Function Serial Peripheral Interface (SPI) supporting SBUS/ I 2 C BUS and standard serial protocols SPI for external frequency synthesis tuning .com 14 bit counter for voltage synthesis tuning Up to Six 6-Bit PWM D/A Converters One 8 bits D/A Converter with 7 analog inputs Five interrupt vectors (IRIN/NMI, Timer 1 & 2, VSYNC, PWR/ADC) On-chip clock oscillator 8 Lines by 20 Characters On-Screen Display Generator with 192 Characters in one bank All ROM types are supported by pin-to-pin CSDIP42 EPROM and OTP versions with programmable OSD fonts. The development tool of the ST63T88 and ST63T89 microcontrollers consists of the (Refer to end of Document for Ordering Information) ST638X-EMU2 emulation and development system to be connected via a standard parallel line to an MS-DOS Personal Computer.
DataShee
October 2003
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ST63E88,ST63T88, ST63E89,ST63T89
1 GENERAL DESCRIPTION
Table 28. Device Summary
Device ST63E88 ST63T88 ST63T89 ST63T89 EPROM (Bytes) 20K 20K 20K OTP (Bytes) 20K RAM (Bytes) 256 256 256 256 EEPROM (Bytes) 384 384 384 384 ADC Yes Yes Yes Yes VS Yes Yes Yes Yes D/A 6 6 4 4 Colour Pins 3 3 3 3 Target R0M Devices ST6380, 82, 88 ST6380, 82, 88 ST6381, 83, 89 ST6381, 83, 89
Figure 35. . Block Diagram
PORT A TEST TEST INTERRUPT Inputs DATA ROM USER SELECTABLE DATA RAM 256 Bytes PORT B & A/D inputs PORT C
PA0 - PA7* PB0 - PB6*
IRIN/PC6
USER PROGRAM MEMORY UP TO 20KBytes
Serial Peripheral Interface
PC2, PC4 - PC7* PC0/SCL PC1/SDA PC3/SEN
TIMER 1
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DATA EEPROM 384 Bytes TIMER 2
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PC STACK LEVEL 1 STACK LEVEL 2 STACK LEVEL 3 STACK LEVEL 4 STACK LEVEL 5 STACK LEVEL 6 POWER SUPPLY OSCILLATOR RESET 8 BIT CORE
Digital Watchdog Timer D/A Outputs DA0 - DA5
VS Output On-Screen Display
VS* R, G, B, BLANK HSYNC, VSYNC
VDD VSS
OSCin OSCout
RESET
OSDOSCout
OSDOSCin VR01753
*Refer to Pin Description for Additional Information
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ST63E88,ST63T88, ST63E89,ST63T89
1.1 PIN DESCRIPTION VDD and VSS. Power is supplied to the MCU using open-drain (5V drive) in output mode while PC4 to these two pins. V DD is power and VSS is the PC7 are open-drain with 12V drive and the input ground connection. pull-up options does not exist on these four pins. PC0, PC1 and PC3 lines when in output mode are OSCin, OSCout. These pins are internally con"ANDed" with the SPI control signals and are all nected to the on-chip oscillator circuit. A quartz open-drain. PC0 is connected to the SPI clock sigcrystal or a ceramic resonator can be connected nal (SCL), PC1 with the SPI data signal (SDA) between these two pins in order to allow the corwhile PC3 is connected with SPI enable signal rect operation of the MCU with various stability/ (SEN, used in S-BUS protocol). Pin PC4 and PC6 cost trade-offs. The OSCin pin is the input pin, the can also be inputs to software programmable edge OSCout pin is the output pin. sensitive latches which can generate interrupts; RESET. The active low RESET pin is used to start PC4 can be connected to Power Interrupt while the microcontroller to the beginning of its program. PC6 can be connected to the IRIN/NMI interrupt Additionally the quartz crystal oscillator will be disline. abled when the RESET pin is low to reduce power DA0-DA5. These pins are the six PWM D/A outconsumption during reset phase. puts of the 6-bit on-chip D/A converters. These TEST/VPP. The TEST pin must be held at VSS for lines have open-drain outputs with 12V drive. The normal operation. output repetition rate is 31.25KHz (with 8MHz clock). If this pin is connected to a +12.5V level during the reset phase, the EPROM programming mode is OSDOSCin, OSDOSCout. These are the On entered. Screen Display oscillator terminals. An oscillation capacitor and coil network have to be connected to PA0-PA7. These 8 lines are organized as one I/O provide the right signal to the OSD. port (A). Each line may be configured as either an input with or without pull-up resistor or as an outHSYNC, VSYNC. These are the horizontal and put under software control of the data direction vertical synchronization pins. The active polarity of register. Pins PA4 to PA7 are configured as openthese pins to the OSD macrocell can be selected drain outputs (12V drive). On PA4-PA7 pins.comuser as ROM mask option. If the device is the inby the put pull-up option is not available while PA6 and specified to have negative logic inputs, then these PA7 have additional current driving capability signals are low the OSD oscillator stops. If the de(25mA, VOL:1V). PA0 to PA3 pins are configured vice is specified to have positive logic inputs, then as push-pull. when these signals are high the OSD oscillator stops. VSYNC is also con-nected to the VSYNC PB0-PB6. These 7 lines are organized as one I/O interrupt. port (B). Each line may be configured as either an input with or without internal pull-up resistor or as R, G, B, BLANK. Outputs from the OSD. R, G and an output under software control of the data direcB are the color outputs while BLANK is the blanktion register. In addition any pin can be configured ing output. All outputs are push-pull. The active by software as the input to the Analog to Digital polarity of these pins can be selected by the user converter. In this case only one pin should be conas ROM mask option. figured at any time to avoid conflicts. VS. This is the output pin of the on-chip 14-bit voltPC0-PC7. These 8 lines are organized as one I/O age synthesis tuning cell (VS). The tuning signal port (C). Each line may be configured as either an present at this pin gives an approximate resolution input with or without internal pull-up resistor or as of 40KHz per step over the UHF band. This line is an output under software control of the data direca push-pull output with standard drive. tion register. Pins PC0 to PC3 are configured as
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ST63E88,ST63T88, ST63E89,ST63T89
Figure 36. ST63E88, T88 Pin configuration
DA0 DA1 DA2 DA3 DA4 DA5 AD1/PB1 AD2/PB2 AD3/PB3 AD4/PB4 AD5/PB5 AD6/PB6 PA0 PA1 PA2 PA3 PA4 PA5 PA6 (HD0) PA7 (HD1) VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VDD PC0/SCL PC1/SDA PC2 PC3/SEN PC4/PWRIN PC5 PC6/IRIN VS RESET OSCout OSCin TEST/VPP (1) OSDOSCout OSDOSCin VSYNC HSYNC BLANK B G R
VR01375
Figure 37. ST63E89, T89 Pin configuration
VS DA1 DA2 DA3 DA4 AD0/PB0 AD1/PB1 AD2/PB2 AD3/PB3 AD4/PB4 AD5/PB5 AD6/PB6 PA0 PA1 PA2 PA3 PA4 PA5 PA6 (HD0) PA7 (HD1) VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VDD PC0/SCL PC1/SDA PC2 PC3/SEN PC4/PWRIN PC5 PC6/IRIN PC7 RESET OSCout OSCin TEST/VPP (1) OSDOSCout OSDOSCin VSYNC HSYNC BLANK B G R
VR01375E
(1) This pin is also the VPP input for OTP/EPROM devices
(1) This pin is also the VPP input for OTP/EPROM devices
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Table 29. Pin Summary
Pin Function DA0 to DA5 VS R, G, B, BLANK HSYNC, VSYNC OSDOSCin OSDOSCout TEST OSCin OSCout RESET PA0- PA3 PA4- PA5 PA6- PA7 PB0- PB6 PC0- PC3 PC4- PC7 VDD, VSS
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Description Output, Open- Drain, 12V Output, Push- Pull Output, Push- Pull Input, Pull- up, Schmitt Trigger Input, High Impedance Output, Push- Pull Input, Pull- Down Input, Resistive Bias, Schmitt Trigger to Reset Logic Only Output, Push- Pull Input, Pull- up, Schmitt Trigger Input I/ O, Push- Pull, Software Input Pull- up, Schmitt Trigger Input I/ O, Open- Drain, 12V, No Input Pull- up, Schmitt Trigger Input I/ O, Open- Drain, 12V, No Input Pull- up, Schmitt Trigger Input, High Drive I/ O, Push- Pull, Software Input Pull- up, Schmitt Trigger Input, Analog input I/ O, Open- Drain, 5V, Software Input Pull- up, Schmitt Trigger Input I/ O, Open- Drain, 12V, No Input Pull- up, Schmitt Trigger Input Power Supply Pins
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ST63E88,ST63T88, ST63E89,ST63T89
1.2 EPROM/OTP DESCRIPTION The ST63E88 and ST63E89 are the EPROM version of the ST6380, 82, 88 and ST6381, 83, 89 ROM products. They are intended for use during the development of an application, and for pre-production and small volume production. The ST63T88 and ST63T89 OTPs have the same characteristics. They both include EPROM memory instead of the ROM memory of the ST6388, 89, and so the program and constants of the program can be easily modified by the user with the ST63E8x EPROM programming board from STMicroelectronics. The EPROM OPTION BYTE is programmed by the EPROM programming board and its associated software. The EPROM Option Byte content will define the OSD options as follows:
7 Opt 1 0 Opt 0
ST63E8x,T8x is described in the User Manual of the EPROM Programming board. On the ST63E88, 89, all the 20140 bytes of PROGRAM memory are available for the user, as all the EPROM memory can be erased by exposure to UV light. On the ST63T88, 89 (OTP device) a reserved area for test purposes exists, as for the ST6388, 89 ROM device. In order to avoid any discrepancy between program functionality when using the EPROM, OTP and ROM it is recommended NOT TO USE THESE RESERVED AREAS, even when using the ST63E88, 89. The Table 4 on page 10 is a summary of the EPROM/ROM Map and its reserved area.
THE READER IS ASKED TO REFER TO THE DATASHEET OF THE ST638x ROM-BASED DEVICE FOR FURTHER DETAILS.
1.3 EPROM ERASING
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The EPROM of the windowed package of the ST63E8, 89 may be erased by exposure to Ultra Violet light. b7-2: Not used. The erasure characteristic of the ST63E88, 89 Opt 1: This option bit disconnect the Schmitt trigEPROM is such that erasure begins when the ger of PC7 and PB0 to prevent some electro-magmemory is exposed to light with wave lengths netic problems when these pads are not bonded. shorter .com than approximately 4000A. It should be -"0": Schmitt triggers are connected to I/O's inputs. noted that sunlight and some types of fluorescent -"1": Schmitt triggers are disconnected from I/O's lamps have wavelengths in the range 3000inputs. 4000A. It is thus recommended that the window of the ST63E88, 89 package be covered by an Opt 0: This option bit enables or disables the Power On/Off Reset. opaque label to prevent unintentional erasure problems when testing the application in such an -"0": The Power On/Off Reset is enabled. environment.The recommended erasure proce-"1": The Power On/Off Reset is disabled. dure of the ST63E88, 89 EPROM is exposure to From a user point of view (with the following exshort wave ultraviolet light which has wavelength ceptions) the ST63E8x,T8x products have exactly 2537A. The integrated dose (i.e. UV intensity x exthe same software and hardware features of the posure time) for erasure should be a minimum of ROM version. An additional mode is used to con15 W-sec/cm2. The erasure time with this dosage figure the part for programming of the EPROM, is approximately 15 to 20 minutes using an ultravithis is set by a +12.5V voltage applied to the olet lamp with 12000mW/cm2 power rating. The TEST/VPP pin. The programming of the ST63E88, 89 should be placed within 2.5cm (1 inch) of the lamp tubes during erasure.
DataShee
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ST63E88,ST63T88, ST63E89,ST63T89
2 ELECTRICAL CHARACTERISTICS
2.1 ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs against damage due to high static voltages, however it is advised to take normal precaution to avoid application of any voltage higher than maximum rated voltages. For proper operation it is recommended that VI and VO must be higher than VSS and smaller than VDD. Reliability is enhanced if unused inputs are connected to an appropriated logic voltage level (VDD or VSS). Power Considerations.The average chip-junction temperature, Tj, in Celsius can be obtained from: Tj= TA + PD x RthJA Where:TA = Ambient Temperature. RthJA = Package thermal resistance (junction-to ambient). PD = Pint + Pport. Pint = IDD x V DD (chip internal power). Pport = Port power dissipation (determined by the user).
Value -0.3 to 7.0 VSS - 0.3 to +13 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to +13 VSS - 0.3 to VDD + 0.3 - 0.3 to 13.0 + 10 + 50 50 150 150 Unit V V V V V V mA mA mA mA C
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Symbol VDD VI VI VO VO VPP IO IO IVDD IVSS Tj
Parameter Supply Voltage Input Voltage (AFC IN) Input Voltage (Other inputs) Output Voltage (PA4-PA7, PC4-PC7, DA0-DA5) Output Voltage (Other outputs) EPROM Programming Voltage Current Drain per Pin Excluding VDD, VSS , PA6, PA7 Current Drain per Pin (PA6, PA7) .com Total Current into VDD (source) Total Current out of VSS (sink) Junction Temperature
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THERMAL CHARACTERISTICS
Symbol RthJA Parameter Thermal Resistance Test Conditions PSDIP42 Min. Value Typ. Max. 67 Unit C/W
2.2 RECOMMENDED OPERATING CONDITIONS
Symbol TA VDD VPP fOSC fOSDOSC Parameter Operating Temperature Operating Supply Voltage EPROM Programming Voltage Oscillator Frequency RUN & WAIT Modes On-screen Display Oscillator Frequency Test Conditions Min. 0 4.5 12.0 Value Typ. 5.0 12.5 8.0 Max. 70 6.0 13.0 8.1 8.0 Unit C V V MHz MHz
EEPROM INFORMATION The ST63xx EEPROM single poly process has been specially developed to achieve 300.000 Write/Erase cycles and a 10 years data retention.
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ST63E88,ST63T88, ST63E89,ST63T89
2.3 DC ELECTRICAL CHARACTERISTICS (TA = 0 to +70C unless otherwise specified). Table 30: DC ELECTRICAL CHARACTERISTICS
Symbol VIL VIH VHYS Parameter Input Low Level Voltage Input High Level Voltage Hysteresis Voltage(1) Test Conditions All I/O Pins All I/O Pins All I/O Pins VDD = 5V DA0-DA5, PB0-PB6, OSD Outputs, PC0-PC7, O0, O1, PA0-PA5 VDD = 4.5V IOL= 1.6mA IOL= 5.0mA PA6-PA7 VDD = 4.5V IOL= 1.6mA IOL= 25mA OSDOSCout OSCout VDD = 4.5V IOL= 0.4mA VS Output VDD = 4.5V IOL= 0.5mA .com IOL= 1.6mA PB0-PB6 PA0-PA3, OSD Outputs VDD = 4.5V IOH = - 1.6mA OSDOSCout, OSCout, VDD = 4.5V IOH= - 0.4mA VS Output VDD = 4.5V IOH= - 0.5mA PB0-PB6, PA0-PA3, PC0-PC3, VIN= VSS OSCin VIN= VSS VIN= VDD OSCin All I/O Input Mode no pull-up OSDOSCin VIN= VDD or VSS Value Typ. Unit V V V
Min. 0.8xVDD
Max. 0.2xVDD
1.0
VOL
Low Level Output Voltage
0.4 1.0
V V
VOL
Low Level Output Voltage
0.4 1.0 0.4
V V V
VOL
Low Level Output Voltage
VOL
Low Level Output Voltage
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VOH High Level Output Voltage
0.4 1.0 4.1
V V V
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VOH
High Level Output Voltage
4.1
V
VOH
High Level Output Voltage Input Pull Up Current Input Mode with Pull-up Input Leakage Current Input Pull-down current in RESET Input Leakage Current RAM Retention Voltage in RESET Input Leakage Current
4.1
V
IPU IIL IIH IIL IIL IIH VDDRAM IIL IIH
- 100
- 50
- 25
mA
- 10 0.1 100
-1 1
- 0.1 10
A A A
-10
10
A
1.5 Reset Pin with Pull-up VIN= VSS - 50 - 30 - 10
V A
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ST63E88,ST63T88, ST63E89,ST63T89
Table 30: DC ELECTRICAL CHARACTERISTICS
Symbol IIL IIH Parameter Test Conditions AFC Pin VIH= VDD VIL= VSS VIH = 12.0V DA0-DA5, PA4-PA5, PC0-PC7, O0, O1 VOH = VDD DA0-DA5, PA4-PA7, PC4-PC7, O0, O1 VOH = 12V fOSC= 8MHz, ILoad= 0mA VDD= 6.0V fOSC= 8MHz, ILoad= 0mA VDD= 6V fOSC= Not App, ILoad= 0mA VDD= 6V RESET Pin RESET Pin A/D AFC Pin VDD= 5V A/D AFC Pin .com Relative to other levels VDD= 5V 0.8xVDD 200 100 Value Typ. Unit
Min.
Max. 1
Input Leakage Current
-1 40 10
A
IOH
Output Leakage Current Output Leakage Current High Voltage Supply Current RUN Mode Supply Current WAIT Mode Supply Current at transition to RESET Reset Trigger Level ON Reset Trigger Level OFF Input Level Absolute Tolerance Input Level Relatice Tolerance(1)
A A mA mA mA V V mV mV
IOH IDD IDD IDD VON VOFF VTA
40 6 3 0.1 16 10 1 0.3xVDD
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VTR
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Note 1. Not 100% Tested
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ST63E88,ST63T88, ST63E89,ST63T89
2.4 AC ELECTRICAL CHARACTERISTICS (TA = 0 to +70C, fOSC=8MHz, VDD=4.5 to 6.0V unless otherwise specified)
Symbol tWRES tOHL tOHL Parameter Minimum Pulse Width High to Low Transition Time High to Low Transition Time Test Conditions RESET Pin PA6, PA7 VDD = 5V, CL = 1000pF (2) DA0-DA5, PB0-PB6, OSD Outputs, PC0-PC7 VDD = 5V, CL = 100pF (2) PB0-PB6, PA0-PA3, OSD Outputs, PC0-PC3 VDD = 5V, CL = 100pF PB0-PB6, PA0-PA3, OSD Outputs, PC0-PC3 VDD = 5V, CL = 100pF Min. 125 Value Typ. Max. Unit ns 100 20 ns ns
tOLH
Low to High Transition Time
20
ns
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Data HOLD Time SPI after clock goes low ICBUS/S-BUS only D/A Converter Repetition FrefDA quency (1) SIO Baudrate (1) fSIO EEPROM Write Time tWEE EEPROM WRITE/ERASE CyEndurance cles Retention EEPROM Data Retention (4) Input Capacitance (3) CIN COUT Output Capacitance (3) COSCin, Oscillator Pins Internal (3) COSCout Capacitance tOH COSDin, Oscillator Pins External COSDout Capacitance
175 31.25 62.50 5 >1 million
ns kHz kHz ms cycles years pF pF pF 25 pF
TA = 25C One Byte QA LOT Acceptance Criteria TA = 25C All Inputs Pins All Outputs Pins
10
300,000 10
10 10 5 15
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DataShee
Notes: 1. A clock other than 8MHz will affect the frequency response of those peripherals (D/A, and SPIs) whose clock is derived from the system clock. 2. The rise and fall times of PORT A have been increased in order to avoid current spikes while maintaining a high drive capability 3. Not 100% Tested 4. Based on extrapolated data
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ST63E88,ST63T88, ST63E89,ST63T89
2.5 OSD TEST CHARACTER IN ORDER TO ALLOW THE TESTING OF THE ON-CHIP OSD MACROCELL THE FOLLOWING CHARACTER MUST BE PROVIDED AT THE FIXED 3Fh (63) POSITION OF THE SECOND OSD BANK. Listing Generation & Verification. When STMicroelectronics receives the files, a computer listing is generated from them. This listing refers extractly to the mask that will be used to produce the microcontroller. Then the listing is returned to the customer that must thoroughly check, complete, sign and return it to STMicroelectronics. The signed list constitutes a part of the contractual agreement for the creation of the customer mask. STMicroelectronics sales organization will provide detailed information on contractual points. Figure 38. OSD Test Character
1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 2 3 4 5 6 7 8 9 10 11 12 13 14
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c)2003 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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